Boomerang: disassembler.m Source File

00001 /*
00002  * Copyright (C) 2002, Sun Microsystems, Inc
00003  *
00004  * See the file "LICENSE.TERMS" for information on usage and
00005  * redistribution of this file, and for a DISCLAIMER OF ALL
00006  * WARRANTIES.
00007  *
00008  */
00009 
00010 /*==============================================================================
00011  * FILE:       disassembler.m
00012  * OVERVIEW:   disassembler skeleton file for x86 SLED specification
00013  *
00014  * Created: 7 Jan 02 - Cristina, based on machine/pentium/decoder_low.m and 
00015  *             machine/sparc/disassembler.m
00016  *============================================================================*/
00017 
00018 
00019 #include "global.h"
00020 #include "decoder.h"
00021 
00022 
00023 /*==============================================================================
00024  * FUNCTION:       NJMCDecoder::decodeAssemblyInstruction
00025  * OVERVIEW:       Decodes a machine instruction and displays its assembly
00026  *                 representation onto the external array _assembly[].
00027  * PARAMETERS:     pc - the native address of the pc
00028  *                 delta - the difference between the native address and
00029  *                  the host address of the pc
00030  * RETURNS:        number of bytes taken up by the decoded instruction
00031  *                  (i.e. number of bytes processed)
00032  *============================================================================*/
00033 int NJMCDecoder::decodeAssemblyInstruction (ADDRESS pc, int delta)
00034 {
00035     ADDRESS hostPC = pc + delta; 
00036     ADDRESS nextPC; 
00037 
00038     sprintf(_assembly, "%X: %08X  ", pc, getDword(hostPC) );
00039     char* str = _assembly + strlen(_assembly);
00040 
00041     match  hostPC to
00042 
00043     | XLATB() =>
00044         sprintf (str, "%s", "XLATB");
00045 
00046     | XCHG.Ev.Gvod(Eaddr, reg) =>
00047         sprintf (str, "%s %s,%s", "XCHG.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00048 
00049     | XCHG.Ev.Gvow(Eaddr, reg) =>
00050         sprintf (str, "%s %s,%s", "XCHG.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00051 
00052     | XCHG.Eb.Gb(Eaddr, reg) =>
00053         sprintf (str, "%s %s,%s", "XCHG.Eb.Gb", DIS_EADDR8, DIS_REG8);
00054 
00055     | NOP() =>
00056         sprintf (str, "%s", "NOP");
00057 
00058     | SEG.FS()  =>   
00059         sprintf (str, "%s", name);
00060 
00061     | SEG.GS()  =>
00062         sprintf (str, "%s", name);
00063 
00064     | XCHGeAXod(r32) =>
00065         sprintf (str,  "XCHGeAXod", DIS_R32);
00066 
00067     | XCHGeAXow(r32) =>
00068         sprintf (str,  "XCHGeAXow", DIS_R32);
00069 
00070     | XADD.Ev.Gvod(Eaddr, reg) =>
00071         sprintf (str,  "XADD.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00072 
00073     | XADD.Ev.Gvow(Eaddr, reg) =>
00074         sprintf (str,  "XADD.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00075 
00076     | XADD.Eb.Gb(Eaddr, reg) =>
00077         sprintf (str,  "XADD.Eb.Gb", DIS_EADDR8, DIS_REG8);
00078 
00079     | WRMSR() =>
00080         sprintf (str,  "WRMSR");
00081 
00082     | WBINVD() =>
00083         sprintf (str,  "WBINVD");
00084 
00085     | WAIT() =>
00086         sprintf (str,  "WAIT");
00087 
00088     | VERW(Eaddr) =>
00089         sprintf (str,  "VERW", DIS_EADDR32);
00090 
00091     | VERR(Eaddr) =>
00092         sprintf (str,  "VERR", DIS_EADDR32);
00093 
00094     | TEST.Ev.Gvod(Eaddr, reg) =>
00095         sprintf (str,  "TEST.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00096 
00097     | TEST.Ev.Gvow(Eaddr, reg) =>
00098         sprintf (str,  "TEST.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00099 
00100     | TEST.Eb.Gb(Eaddr, reg) =>
00101         sprintf (str,  "TEST.Eb.Gb", DIS_EADDR8, DIS_REG8);
00102 
00103     | TEST.Ed.Id(Eaddr, i32) =>
00104         sprintf (str,  "TEST.Ed.Id", DIS_EADDR32, DIS_I32);
00105 
00106     | TEST.Ew.Iw(Eaddr, i16) =>
00107         sprintf (str,  "TEST.Ew.Iw", DIS_EADDR16, DIS_I16);
00108 
00109     | TEST.Eb.Ib(Eaddr, i8) =>
00110         sprintf (str,  "TEST.Eb.Ib", DIS_EADDR8, DIS_I8);
00111 
00112     | TEST.eAX.Ivod(i32) =>
00113         sprintf (str,  "TEST.eAX.Ivod", DIS_I32);
00114 
00115     | TEST.eAX.Ivow(i16) =>
00116         sprintf (str,  "TEST.eAX.Ivow", DIS_I16);
00117 
00118     | TEST.AL.Ib(i8) =>
00119         sprintf (str,  "TEST.AL.Ib", DIS_I8);
00120 
00121     | STR(Mem) =>
00122         sprintf (str,  "STR", DIS_MEM);
00123 
00124     | STOSvod() =>
00125         sprintf (str,  "STOSvod");
00126 
00127     | STOSvow() =>
00128         sprintf (str,  "STOSvow");
00129 
00130     | STOSB() =>
00131         sprintf (str,  "STOSB");
00132 
00133     | STI() =>
00134         sprintf (str,  "STI");
00135 
00136     | STD() =>
00137         sprintf (str,  "STD");
00138 
00139     | STC() =>
00140         sprintf (str,  "STC");
00141 
00142     | SMSW(Eaddr) =>
00143         sprintf (str,  "SMSW", DIS_EADDR32);
00144 
00145     | SLDT(Eaddr) =>
00146         sprintf (str,  "SLDT", DIS_EADDR32);
00147 
00148     | SHLD.CLod(Eaddr, reg) =>
00149         sprintf (str,  "SHLD.CLod", DIS_EADDR32, DIS_REG32);
00150 
00151     | SHLD.CLow(Eaddr, reg) =>
00152         sprintf (str,  "SHLD.CLow", DIS_EADDR16, DIS_REG16);
00153 
00154     | SHRD.CLod(Eaddr, reg) =>
00155         sprintf (str,  "SHRD.CLod", DIS_EADDR32, DIS_REG32);
00156 
00157     | SHRD.CLow(Eaddr, reg) =>
00158         sprintf (str,  "SHRD.CLow", DIS_EADDR16, DIS_REG16);
00159 
00160     | SHLD.Ibod(Eaddr, reg, count) =>
00161         sprintf (str,  "SHLD.Ibod", DIS_EADDR32, DIS_REG32, DIS_COUNT);
00162 
00163     | SHLD.Ibow(Eaddr, reg, count) =>
00164         sprintf (str,  "SHLD.Ibow", DIS_EADDR16, DIS_REG16, DIS_COUNT);
00165 
00166     | SHRD.Ibod(Eaddr, reg, count) =>
00167         sprintf (str,  "SHRD.Ibod", DIS_EADDR32, DIS_REG32, DIS_COUNT);
00168 
00169     | SHRD.Ibow(Eaddr, reg, count) =>
00170         sprintf (str,  "SHRD.Ibow", DIS_EADDR16, DIS_REG16, DIS_COUNT);
00171 
00172     | SIDT(Mem) =>
00173         sprintf (str,  "SIDT", DIS_MEM);
00174 
00175     | SGDT(Mem) =>
00176         sprintf (str,  "SGDT", DIS_MEM);
00177 
00178     // Sets are now in the high level instructions
00179     | SCASvod() =>
00180         sprintf (str,  "SCASvod");
00181 
00182     | SCASvow() =>
00183         sprintf (str,  "SCASvow");
00184 
00185     | SCASB() =>
00186         sprintf (str,  "SCASB");
00187 
00188     | SAHF() =>
00189         sprintf (str,  "SAHF");
00190 
00191     | RSM() =>
00192         sprintf (str,  "RSM");
00193 
00194     | RET.far.Iw(i16) =>
00195         sprintf (str,  "RET.far.Iw", DIS_I16);
00196 
00197     | RET.Iw(i16) =>
00198         sprintf (str,  "RET.Iw", DIS_I16);
00199 
00200     | RET.far() =>
00201         sprintf (str,  "RET.far");
00202 
00203     | RET() =>
00204         sprintf (str,  "RET");
00205 
00206 //   | REPNE() =>
00207 //      sprintf (str,  "REPNE");
00208 
00209 //  | REP() =>
00210 //      sprintf (str,  "REP");
00211 
00212     | REP.CMPSB()  =>
00213         sprintf (str,  name);
00214 
00215     | REP.CMPSvow()  =>
00216         sprintf (str,  name);
00217 
00218     | REP.CMPSvod()  =>
00219         sprintf (str,  name);
00220 
00221     | REP.LODSB()  =>
00222         sprintf (str,  name);
00223 
00224     | REP.LODSvow()  =>
00225         sprintf (str,  name);
00226 
00227     | REP.LODSvod()  =>
00228         sprintf (str,  name);
00229 
00230     | REP.MOVSB()  =>
00231         sprintf (str,  name);
00232 
00233     | REP.MOVSvow()  =>
00234         sprintf (str,  name);
00235 
00236     | REP.MOVSvod()  =>
00237         sprintf (str,  name);
00238 
00239     | REP.SCASB()  =>
00240         sprintf (str,  name);
00241 
00242     | REP.SCASvow()  =>
00243         sprintf (str,  name);
00244 
00245     | REP.SCASvod()  =>
00246         sprintf (str,  name);
00247 
00248     | REP.STOSB()  =>
00249         sprintf (str,  name);
00250 
00251     | REP.STOSvow()  =>
00252         sprintf (str,  name);
00253 
00254     | REP.STOSvod()  =>
00255         sprintf (str,  name);
00256 
00257     | REPNE.CMPSB()  =>
00258         sprintf (str,  name);
00259 
00260     | REPNE.CMPSvow()  =>
00261         sprintf (str,  name);
00262 
00263     | REPNE.CMPSvod()  =>
00264         sprintf (str,  name);
00265 
00266     | REPNE.LODSB()  =>
00267         sprintf (str,  name);
00268 
00269     | REPNE.LODSvow()  =>
00270         sprintf (str,  name);
00271 
00272     | REPNE.LODSvod()  =>
00273         sprintf (str,  name);
00274 
00275     | REPNE.MOVSB()  =>
00276         sprintf (str,  name);
00277 
00278     | REPNE.MOVSvow()  =>
00279         sprintf (str,  name);
00280 
00281     | REPNE.MOVSvod()  =>
00282         sprintf (str,  name);
00283 
00284     | REPNE.SCASB()  =>
00285         sprintf (str,  name);
00286 
00287     | REPNE.SCASvow()  =>
00288         sprintf (str,  name);
00289 
00290     | REPNE.SCASvod()  =>
00291         sprintf (str,  name);
00292 
00293     | REPNE.STOSB()  =>
00294         sprintf (str,  name);
00295 
00296     | REPNE.STOSvow()  =>
00297         sprintf (str,  name);
00298 
00299     | REPNE.STOSvod()  =>
00300         sprintf (str,  name);
00301 
00302     | RDMSR() =>
00303         sprintf (str,  "RDMSR");
00304 
00305     | SARB.Ev.Ibod(Eaddr, i8) =>
00306         sprintf (str,  "SARB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00307 
00308     | SARB.Ev.Ibow(Eaddr, i8) =>
00309         sprintf (str,  "SARB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00310 
00311     | SHRB.Ev.Ibod(Eaddr, i8) =>
00312         sprintf (str,  "SHRB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00313 
00314     | SHRB.Ev.Ibow(Eaddr, i8) =>
00315         sprintf (str,  "SHRB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00316 
00317     | SHLSALB.Ev.Ibod(Eaddr, i8) =>
00318         sprintf (str,  "SHLSALB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00319 
00320     | SHLSALB.Ev.Ibow(Eaddr, i8) =>
00321         sprintf (str,  "SHLSALB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00322 
00323     | RCRB.Ev.Ibod(Eaddr, i8) =>
00324         sprintf (str,  "RCRB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00325 
00326     | RCRB.Ev.Ibow(Eaddr, i8) =>
00327         sprintf (str,  "RCRB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00328 
00329     | RCLB.Ev.Ibod(Eaddr, i8) =>
00330         sprintf (str,  "RCLB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00331 
00332     | RCLB.Ev.Ibow(Eaddr, i8) =>
00333         sprintf (str,  "RCLB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00334 
00335     | RORB.Ev.Ibod(Eaddr, i8) =>
00336         sprintf (str,  "RORB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00337 
00338     | RORB.Ev.Ibow(Eaddr, i8) =>
00339         sprintf (str,  "RORB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00340 
00341     | ROLB.Ev.Ibod(Eaddr, i8) =>
00342         sprintf (str,  "ROLB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00343 
00344     | ROLB.Ev.Ibow(Eaddr, i8) =>
00345         sprintf (str,  "ROLB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00346 
00347     | SARB.Eb.Ib(Eaddr, i8) =>
00348         sprintf (str,  "SARB.Eb.Ib", DIS_EADDR8, DIS_I8);
00349 
00350     | SHRB.Eb.Ib(Eaddr, i8) =>
00351         sprintf (str,  "SHRB.Eb.Ib", DIS_EADDR8, DIS_I8);
00352 
00353     | SHLSALB.Eb.Ib(Eaddr, i8) =>
00354         sprintf (str,  "SHLSALB.Eb.Ib", DIS_EADDR8, DIS_I8);
00355 
00356     | RCRB.Eb.Ib(Eaddr, i8) =>
00357         sprintf (str,  "RCRB.Eb.Ib", DIS_EADDR8, DIS_I8);
00358 
00359     | RCLB.Eb.Ib(Eaddr, i8) =>
00360         sprintf (str,  "RCLB.Eb.Ib", DIS_EADDR8, DIS_I8);
00361 
00362     | RORB.Eb.Ib(Eaddr, i8) =>
00363         sprintf (str,  "RORB.Eb.Ib", DIS_EADDR8, DIS_I8);
00364 
00365     | ROLB.Eb.Ib(Eaddr, i8) =>
00366         sprintf (str,  "ROLB.Eb.Ib", DIS_EADDR8, DIS_I8);
00367 
00368     | SARB.Ev.CLod(Eaddr) =>
00369         sprintf (str,  "SARB.Ev.CLod", DIS_EADDR32);
00370 
00371     | SARB.Ev.CLow(Eaddr) =>
00372         sprintf (str,  "SARB.Ev.CLow", DIS_EADDR16);
00373 
00374     | SARB.Ev.1od(Eaddr) =>
00375         sprintf (str,  "SARB.Ev.1od", DIS_EADDR32);
00376 
00377     | SARB.Ev.1ow(Eaddr) =>
00378         sprintf (str,  "SARB.Ev.1ow", DIS_EADDR16);
00379 
00380     | SHRB.Ev.CLod(Eaddr) =>
00381         sprintf (str,  "SHRB.Ev.CLod", DIS_EADDR32);
00382 
00383     | SHRB.Ev.CLow(Eaddr) =>
00384         sprintf (str,  "SHRB.Ev.CLow", DIS_EADDR16);
00385 
00386     | SHRB.Ev.1od(Eaddr) =>
00387         sprintf (str,  "SHRB.Ev.1od", DIS_EADDR32);
00388 
00389     | SHRB.Ev.1ow(Eaddr) =>
00390         sprintf (str,  "SHRB.Ev.1ow", DIS_EADDR16);
00391 
00392     | SHLSALB.Ev.CLod(Eaddr) =>
00393         sprintf (str,  "SHLSALB.Ev.CLod", DIS_EADDR32);
00394 
00395     | SHLSALB.Ev.CLow(Eaddr) =>
00396         sprintf (str,  "SHLSALB.Ev.CLow", DIS_EADDR16);
00397 
00398     | SHLSALB.Ev.1od(Eaddr) =>
00399         sprintf (str,  "SHLSALB.Ev.1od", DIS_EADDR32);
00400 
00401     | SHLSALB.Ev.1ow(Eaddr) =>
00402         sprintf (str,  "SHLSALB.Ev.1ow", DIS_EADDR16);
00403 
00404     | RCRB.Ev.CLod(Eaddr) =>
00405         sprintf (str,  "RCRB.Ev.CLod", DIS_EADDR32);
00406 
00407     | RCRB.Ev.CLow(Eaddr) =>
00408         sprintf (str,  "RCRB.Ev.CLow", DIS_EADDR16);
00409 
00410     | RCRB.Ev.1od(Eaddr) =>
00411         sprintf (str,  "RCRB.Ev.1od", DIS_EADDR32);
00412 
00413     | RCRB.Ev.1ow(Eaddr) =>
00414         sprintf (str,  "RCRB.Ev.1ow", DIS_EADDR16);
00415 
00416     | RCLB.Ev.CLod(Eaddr) =>
00417         sprintf (str,  "RCLB.Ev.CLod", DIS_EADDR32);
00418 
00419     | RCLB.Ev.CLow(Eaddr) =>
00420         sprintf (str,  "RCLB.Ev.CLow", DIS_EADDR16);
00421 
00422     | RCLB.Ev.1od(Eaddr) =>
00423         sprintf (str,  "RCLB.Ev.1od", DIS_EADDR32);
00424 
00425     | RCLB.Ev.1ow(Eaddr) =>
00426         sprintf (str,  "RCLB.Ev.1ow", DIS_EADDR16);
00427 
00428     | RORB.Ev.CLod(Eaddr) =>
00429         sprintf (str,  "RORB.Ev.CLod", DIS_EADDR32);
00430 
00431     | RORB.Ev.CLow(Eaddr) =>
00432         sprintf (str,  "RORB.Ev.CLow", DIS_EADDR16);
00433 
00434     | RORB.Ev.1od(Eaddr) =>
00435         sprintf (str,  "RORB.Ev.1od", DIS_EADDR32);
00436 
00437     | RORB.Ev.1ow(Eaddr) =>
00438         sprintf (str,  "ORB.Ev.1owR", DIS_EADDR16);
00439 
00440     | ROLB.Ev.CLod(Eaddr) =>
00441         sprintf (str,  "ROLB.Ev.CLod", DIS_EADDR32);
00442 
00443     | ROLB.Ev.CLow(Eaddr) =>
00444         sprintf (str,  "ROLB.Ev.CLow", DIS_EADDR16);
00445 
00446     | ROLB.Ev.1od(Eaddr) =>
00447         sprintf (str,  "ROLB.Ev.1od", DIS_EADDR32);
00448 
00449     | ROLB.Ev.1ow(Eaddr) =>
00450         sprintf (str,  "ROLB.Ev.1ow", DIS_EADDR16);
00451 
00452     | SARB.Eb.CL(Eaddr) =>
00453         sprintf (str,  "SARB.Eb.CL", DIS_EADDR32);
00454 
00455     | SARB.Eb.1(Eaddr) =>
00456         sprintf (str,  "SARB.Eb.1", DIS_EADDR16);
00457 
00458     | SHRB.Eb.CL(Eaddr) =>
00459         sprintf (str,  "SHRB.Eb.CL", DIS_EADDR8);
00460 
00461     | SHRB.Eb.1(Eaddr) =>
00462         sprintf (str,  "SHRB.Eb.1", DIS_EADDR8);
00463 
00464     | SHLSALB.Eb.CL(Eaddr) =>
00465         sprintf (str,  "SHLSALB.Eb.CL", DIS_EADDR8);
00466 
00467     | SHLSALB.Eb.1(Eaddr) =>
00468         sprintf (str,  "SHLSALB.Eb.1", DIS_EADDR8);
00469 
00470     | RCRB.Eb.CL(Eaddr) =>
00471         sprintf (str,  "RCRB.Eb.CL", DIS_EADDR8);
00472 
00473     | RCRB.Eb.1(Eaddr) =>
00474         sprintf (str,  "RCRB.Eb.1", DIS_EADDR8);
00475 
00476     | RCLB.Eb.CL(Eaddr) =>
00477         sprintf (str,  "RCLB.Eb.CL", DIS_EADDR8);
00478 
00479     | RCLB.Eb.1(Eaddr) =>
00480         sprintf (str,  "RCLB.Eb.1", DIS_EADDR8);
00481 
00482     | RORB.Eb.CL(Eaddr) =>
00483         sprintf (str,  "RORB.Eb.CL", DIS_EADDR8);
00484 
00485     | RORB.Eb.1(Eaddr) =>
00486         sprintf (str,  "RORB.Eb.1", DIS_EADDR8);
00487 
00488     | ROLB.Eb.CL(Eaddr) =>
00489         sprintf (str,  "ROLB.Eb.CL", DIS_EADDR8);
00490 
00491     | ROLB.Eb.1(Eaddr) =>
00492         sprintf (str,  "ROLB.Eb.1", DIS_EADDR8);
00493 
00494     | PUSHFod() =>
00495         sprintf (str,  "PUSHFod");
00496 
00497     | PUSHFow() =>
00498         sprintf (str,  "PUSHFow");
00499 
00500 //    | PUSHAod() =>
00501 //        sprintf (str,  "PUSHAod");
00502 
00503 //    | PUSHAow() =>
00504 //        sprintf (str,  "PUSHAow");
00505 
00506     | PUSH.GS() =>
00507         sprintf (str,  "PUSH.GS");
00508 
00509     | PUSH.FS() =>
00510         sprintf (str,  "PUSH.FS");
00511 
00512     | PUSH.ES() =>
00513         sprintf (str,  "PUSH.ES");
00514 
00515     | PUSH.DS() =>
00516         sprintf (str,  "PUSH.DS");
00517 
00518     | PUSH.SS() =>
00519         sprintf (str,  "PUSH.SS");
00520 
00521     | PUSH.CS() =>
00522         sprintf (str,  "PUSH.CS");
00523 
00524     | PUSH.Ivod(i32) =>
00525         sprintf (str,  "PUSH.Ivod", DIS_I32);
00526 
00527     | PUSH.Ivow(i16) =>
00528         sprintf (str,  "PUSH.Ivow", DIS_I16);
00529 
00530     | PUSH.Ixob(i8) =>
00531         sprintf (str,  "PUSH.Ixob", DIS_I8);
00532 
00533     | PUSH.Ixow(i8) =>
00534         sprintf (str,  "PUSH.Ixow", DIS_I8);
00535 
00536     | PUSHod(r32) =>
00537         sprintf (str,  "PUSHod", DIS_R32);
00538 
00539     | PUSHow(r32) =>
00540         sprintf (str,  "PUSHow", DIS_R32);  // Check!
00541 
00542     | PUSH.Evod(Eaddr) =>
00543         sprintf (str,  "PUSH.Evod", DIS_EADDR32);
00544 
00545     | PUSH.Evow(Eaddr) =>
00546         sprintf (str,  "PUSH.Evow", DIS_EADDR16);
00547 
00548     | POPFod() =>
00549         sprintf (str,  "POPFod");
00550 
00551     | POPFow() =>
00552         sprintf (str,  "POPFow");
00553 
00554 //    | POPAod() =>
00555 //        sprintf (str,  "POPAod");
00556 
00557 //    | POPAow() =>
00558 //        sprintf (str,  "POPAow");
00559 
00560     | POP.GS() =>
00561         sprintf (str,  "POP.GS");
00562 
00563     | POP.FS() =>
00564         sprintf (str,  "POP.FS");
00565 
00566     | POP.DS() =>
00567         sprintf (str,  "POP.DS");
00568 
00569     | POP.SS() =>
00570         sprintf (str,  "POP.SS");
00571 
00572     | POP.ES() =>
00573         sprintf (str,  "POP.ES");
00574 
00575     | POPod(r32) =>
00576         sprintf (str,  "POPod", DIS_R32);
00577 
00578     | POPow(r32) =>
00579         sprintf (str,  "POPow", DIS_R32);   // Check!
00580 
00581     | POP.Evod(Mem) =>
00582         sprintf (str,  "POP.Evod", DIS_MEM);
00583 
00584     | POP.Evow(Mem) =>
00585         sprintf (str,  "POP.Evow", DIS_MEM);
00586 
00587 //    | OUTSvod() =>
00588 //        sprintf (str,  "OUTSvod");
00589 
00590 //    | OUTSvow() =>
00591 //        sprintf (str,  "OUTSvow");
00592 
00593 //    | OUTSB() =>
00594 //        sprintf (str,  "OUTSB");
00595 
00596 //    | OUT.DX.eAXod() =>
00597 //        sprintf (str,  "OUT.DX.eAXod");
00598 
00599 //    | OUT.DX.eAXow() =>
00600 //        sprintf (str,  "OUT.DX.eAXow");
00601 
00602 //    | OUT.DX.AL() =>
00603 //        sprintf (str,  "OUT.DX.AL");
00604 
00605 //    | OUT.Ib.eAXod(i8) =>
00606 //        sprintf (str,  "OUT.Ib.eAXod", DIS_I8);
00607 
00608 //    | OUT.Ib.eAXow(i8) =>
00609 //        sprintf (str,  "OUT.Ib.eAXow", DIS_I8);
00610 
00611 //    | OUT.Ib.AL(i8) =>
00612 //        sprintf (str,  "OUT.Ib.AL", DIS_I8);
00613 
00614     | NOTod(Eaddr) =>
00615         sprintf (str,  "NOTod", DIS_EADDR32);
00616 
00617     | NOTow(Eaddr) =>
00618         sprintf (str,  "NOTow", DIS_EADDR16);
00619 
00620     | NOTb(Eaddr) =>
00621         sprintf (str,  "NOTb", DIS_EADDR8);
00622 
00623     | NEGod(Eaddr) =>
00624         sprintf (str,  "NEGod", DIS_EADDR32);
00625 
00626     | NEGow(Eaddr) =>
00627         sprintf (str,  "NEGow", DIS_EADDR16);
00628 
00629     | NEGb(Eaddr) =>
00630         sprintf (str,  "NEGb", DIS_EADDR8);
00631 
00632     | MUL.AXod(Eaddr) =>
00633         sprintf (str,  "MUL.AXod", DIS_EADDR32);
00634 
00635     | MUL.AXow(Eaddr) =>
00636         sprintf (str,  "MUL.AXow", DIS_EADDR16);
00637 
00638     | MUL.AL(Eaddr) =>
00639         sprintf (str,  "MUL.AL", DIS_EADDR8);
00640 
00641     | MOVZX.Gv.Ew(r32, Eaddr) =>
00642         sprintf (str,  "MOVZX.Gv.Ew", DIS_R32, DIS_EADDR16);
00643 
00644     | MOVZX.Gv.Ebod(r32, Eaddr) =>
00645         sprintf (str,  "MOVZX.Gv.Ebod", DIS_R32, DIS_EADDR8);
00646 
00647     | MOVZX.Gv.Ebow(r16, Eaddr) =>
00648         sprintf (str,  "MOVZX.Gv.Ebow", DIS_R16, DIS_EADDR8);
00649 
00650     | MOVSX.Gv.Ew(r32, Eaddr) =>
00651         sprintf (str,  "MOVSX.Gv.Ew", DIS_R32, DIS_EADDR16);
00652 
00653     | MOVSX.Gv.Ebod(r32, Eaddr) =>
00654         sprintf (str,  "MOVSX.Gv.Ebod", DIS_R32, DIS_EADDR8);
00655 
00656     | MOVSX.Gv.Ebow(r16, Eaddr) =>
00657         sprintf (str,  "MOVZX.Gv.Ebow", DIS_R16, DIS_EADDR8);
00658 
00659     | MOVSvod() =>
00660         sprintf (str,  "MOVSvod");
00661 
00662     | MOVSvow() =>
00663         sprintf (str,  "MOVSvow");
00664 
00665     | MOVSB() =>
00666         sprintf (str,  "MOVSB");
00667 
00668 //    | MOV.Rd.Dd(reg, dr) => 
00669 //        unused(reg); unused(dr);
00670 //        sprintf (str,  "UNIMP");
00671 
00672 //    | MOV.Dd.Rd(dr, reg) =>
00673 //        unused(reg); unused(dr);
00674 //        sprintf (str,  "UNIMP");
00675 
00676 //    | MOV.Rd.Cd(reg, cr) =>
00677 //        unused(reg); unused(cr);
00678 //        sprintf (str,  "UNIMP");
00679 
00680 //    | MOV.Cd.Rd(cr, reg) =>
00681 //        unused(reg); unused(cr);
00682 //        sprintf (str,  "UNIMP");
00683 
00684     | MOV.Eb.Ivod(Eaddr, i32) =>
00685         sprintf (str,  "MOV.Eb.Ivod", DIS_EADDR32, DIS_I32);
00686 
00687     | MOV.Eb.Ivow(Eaddr, i16) =>
00688         sprintf (str,  "MOV.Eb.Ivow", DIS_EADDR16, DIS_I16);
00689 
00690     | MOV.Eb.Ib(Eaddr, i8) =>
00691         sprintf (str,  "MOV.Eb.Ib", DIS_EADDR8, DIS_I8);
00692 
00693     | MOVid(r32, i32) =>
00694         sprintf (str,  "MOVid", DIS_R32, DIS_I32);
00695 
00696     | MOViw(r16, i16) =>
00697         sprintf (str,  "MOViw", DIS_R16, DIS_I16);  // Check!
00698 
00699     | MOVib(r8, i8) =>
00700         sprintf (str,  "MOVib", DIS_R8, DIS_I8);
00701 
00702     | MOV.Ov.eAXod(off) =>
00703         sprintf (str,  "MOV.Ov.eAXod", DIS_OFF);
00704 
00705     | MOV.Ov.eAXow(off) =>
00706         sprintf (str,  "MOV.Ov.eAXow", DIS_OFF);
00707 
00708     | MOV.Ob.AL(off) =>
00709         sprintf (str,  "MOV.Ob.AL", DIS_OFF);
00710 
00711     | MOV.eAX.Ovod(off) =>
00712         sprintf (str,  "MOV.eAX.Ovod", DIS_OFF);
00713 
00714     | MOV.eAX.Ovow(off) =>
00715         sprintf (str,  "MOV.eAX.Ovow", DIS_OFF);
00716 
00717     | MOV.AL.Ob(off) =>
00718         sprintf (str,  "MOV.AL.Ob", DIS_OFF);
00719 
00720 //    | MOV.Sw.Ew(Mem, sr16) =>
00721 //        sprintf (str,  "MOV.Sw.Ew", DIS_MEM, DIS_SR16);
00722 
00723 //    | MOV.Ew.Sw(Mem, sr16) =>
00724 //        sprintf (str,  "MOV.Ew.Sw", DIS_MEM, DIS_SR16);
00725 
00726     | MOVrmod(reg, Eaddr) =>
00727         sprintf (str,  "MOVrmod", DIS_REG32, DIS_EADDR32);
00728 
00729     | MOVrmow(reg, Eaddr) =>
00730         sprintf (str,  "MOVrmow", DIS_REG16, DIS_EADDR16);
00731 
00732     | MOVrmb(reg, Eaddr) =>
00733         sprintf (str,  "MOVrmb", DIS_REG8, DIS_EADDR8);
00734 
00735     | MOVmrod(Eaddr, reg) =>
00736         sprintf (str,  "MOVmrod", DIS_EADDR32, DIS_REG32);
00737 
00738     | MOVmrow(Eaddr, reg) =>
00739         sprintf (str,  "MOVmrow", DIS_EADDR16, DIS_REG16);
00740 
00741     | MOVmrb(Eaddr, reg) =>
00742         sprintf (str,  "MOVmrb", DIS_EADDR8, DIS_REG8);
00743 
00744     | LTR(Eaddr) =>
00745         sprintf (str,  "LTR", DIS_EADDR32);
00746 
00747     | LSS(reg, Mem) =>
00748         sprintf (str,  "LSS", DIS_REG32, DIS_MEM);
00749 
00750     | LSLod(reg, Eaddr) =>
00751         sprintf (str,  "LSLod", DIS_REG32, DIS_EADDR32);
00752 
00753     | LSLow(reg, Eaddr) =>
00754         sprintf (str,  "LSLow", DIS_REG16, DIS_EADDR16);
00755 
00756     | LOOPNE(relocd) =>
00757         sprintf (str,  "LOOPNE", dis_Num(relocd - hostPC - 2));
00758 
00759     | LOOPE(relocd) =>
00760         sprintf (str,  "LOOPE", dis_Num(relocd-hostPC-2));
00761 
00762     | LOOP(relocd) =>
00763         sprintf (str,  "LOOP", dis_Num(relocd-hostPC-2));
00764 
00765     | LGS(reg, Mem) =>
00766         sprintf (str,  "LGS", DIS_REG32, DIS_MEM);
00767 
00768     | LFS(reg, Mem) =>
00769         sprintf (str,  "LFS", DIS_REG32, DIS_MEM);
00770 
00771     | LES(reg, Mem) =>
00772         sprintf (str,  "LES", DIS_REG32, DIS_MEM);
00773 
00774     | LEAVE() =>
00775         sprintf (str,  "LEAVE");
00776 
00777     | LEAod(reg, Mem) =>
00778         sprintf (str,  "LEA.od", DIS_REG32, DIS_MEM);
00779 
00780     | LEAow(reg, Mem) =>
00781         sprintf (str,  "LEA.ow", DIS_REG16, DIS_MEM);
00782 
00783     | LDS(reg, Mem) =>
00784         sprintf (str,  "LDS", DIS_REG32, DIS_MEM);
00785 
00786     | LARod(reg, Eaddr) =>
00787         sprintf (str,  "LAR.od", DIS_REG32, DIS_EADDR32);
00788 
00789     | LARow(reg, Eaddr) =>
00790         sprintf (str,  "LAR.ow", DIS_REG16, DIS_EADDR16);
00791 
00792     | LAHF() =>
00793         sprintf (str,  "LAHF");
00794 
00795     /* Branches have been handled in decodeInstruction() now */
00796     | IRET() =>
00797         sprintf (str,  "IRET");
00798 
00799     | INVLPG(Mem) =>
00800         sprintf (str,  "INVLPG", DIS_MEM);
00801 
00802     | INVD() =>
00803         sprintf (str,  "INVD");
00804 
00805     | INTO() =>
00806         sprintf (str,  "INTO");
00807 
00808     | INT.Ib(i8) =>
00809         sprintf (str,  "INT.Ib", DIS_I8);
00810 
00811     | INT3() =>
00812         sprintf (str,  "INT3");
00813 
00814 //    | INSvod() =>
00815 //        sprintf (str,  "INSvod");
00816 
00817 //    | INSvow() =>
00818 //        sprintf (str,  "INSvow");
00819 
00820 //    | INSB() =>
00821 //        sprintf (str,  "INSB");
00822 
00823     | INCod(r32) =>
00824         sprintf (str,  "INCod", DIS_R32);
00825 
00826     | INCow(r32) =>
00827         sprintf (str,  "INCow", DIS_R32);
00828 
00829     | INC.Evod(Eaddr) =>
00830         sprintf (str,  "INC.Evod", DIS_EADDR32);
00831 
00832     | INC.Evow(Eaddr) =>
00833         sprintf (str,  "INC.Evow", DIS_EADDR16);
00834 
00835     | INC.Eb(Eaddr) =>
00836         sprintf (str,  "INC.Eb", DIS_EADDR8);
00837 
00838 //    | IN.eAX.DXod() =>
00839 //        sprintf (str,  "IN.eAX.DXod");
00840 
00841 //    | IN.eAX.DXow() =>
00842 //        sprintf (str,  "IN.eAX.DXow");
00843 
00844 //    | IN.AL.DX() =>
00845 //        sprintf (str,  "IN.AL.DX");
00846 
00847 //    | IN.eAX.Ibod(i8) =>
00848 //        sprintf (str,  "IN.eAX.Ibod", DIS_I8);
00849 
00850 //    | IN.eAX.Ibow(i8) =>
00851 //        sprintf (str,  "IN.eAX.Ibow", DIS_I8);
00852 
00853 //    | IN.AL.Ib(i8) =>
00854 //        sprintf (str,  "IN.AL.Ib", DIS_I8);
00855 
00856     | IMUL.Ivd(reg, Eaddr, i32) =>
00857         sprintf (str,  "IMUL.Ivd", DIS_REG32, DIS_EADDR32, DIS_I32);
00858 
00859     | IMUL.Ivw(reg, Eaddr, i16) =>
00860         sprintf (str,  "IMUL.Ivw", DIS_REG16, DIS_EADDR16, DIS_I16);
00861 
00862     | IMUL.Ibod(reg, Eaddr, i8) =>
00863         sprintf (str,  "IMUL.Ibod", DIS_REG32, DIS_EADDR32, DIS_I8);
00864 
00865     | IMUL.Ibow(reg, Eaddr, i8) =>
00866         sprintf (str,  "IMUL.Ibow", DIS_REG16, DIS_EADDR16, DIS_I8);
00867 
00868     | IMULrmod(reg, Eaddr) =>
00869         sprintf (str,  "IMULrmod", DIS_REG32, DIS_EADDR32);
00870 
00871     | IMULrmow(reg, Eaddr) =>
00872         sprintf (str,  "IMULrmow", DIS_REG16, DIS_EADDR16);
00873 
00874     | IMULod(Eaddr) =>
00875         sprintf (str,  "IMULod", DIS_EADDR32);
00876 
00877     | IMULow(Eaddr) =>
00878         sprintf (str,  "IMULow", DIS_EADDR16);
00879 
00880     | IMULb(Eaddr) =>
00881         sprintf (str,  "IMULb", DIS_EADDR8);
00882 
00883     | IDIVeAX(Eaddr) =>
00884         sprintf (str,  "IDIVeAX", DIS_EADDR32);
00885 
00886     | IDIVAX(Eaddr) =>
00887         sprintf (str,  "IDIVAX", DIS_EADDR16);
00888 
00889     | IDIV(Eaddr) =>
00890         sprintf (str,  "IDIV", DIS_EADDR8); /* ?? */
00891 
00892 //  | HLT() =>
00893 //      sprintf (str,  "HLT");
00894 
00895     | ENTER(i16, i8) =>
00896         sprintf (str,  "ENTER", DIS_I16, DIS_I8);
00897 
00898     | DIVeAX(Eaddr) =>
00899         sprintf (str,  "DIVeAX", DIS_EADDR32);
00900 
00901     | DIVAX(Eaddr) =>
00902         sprintf (str,  "DIVAX", DIS_EADDR16);
00903 
00904     | DIVAL(Eaddr) =>
00905         sprintf (str,  "DIVAL", DIS_EADDR8);
00906 
00907     | DECod(r32) =>
00908         sprintf (str,  "DECod", DIS_R32);
00909 
00910     | DECow(r32) =>
00911         sprintf (str,  "DECow", DIS_R32);
00912 
00913     | DEC.Evod(Eaddr) =>
00914         sprintf (str,  "DEC.Evod", DIS_EADDR32);
00915 
00916     | DEC.Evow(Eaddr) =>
00917         sprintf (str,  "DEC.Evow", DIS_EADDR16);
00918 
00919     | DEC.Eb(Eaddr) =>
00920         sprintf (str,  "DEC.Eb", DIS_EADDR8);
00921 
00922     | DAS() =>
00923         sprintf (str,  "DAS");
00924 
00925     | DAA() =>
00926         sprintf (str,  "DAA");
00927 
00928     | CDQ() =>
00929         sprintf (str,  "CDQ");
00930 
00931     | CWD() =>
00932         sprintf (str,  "CWD");
00933 
00934     | CPUID() =>
00935         sprintf (str,  "CPUID");
00936 
00937     | CMPXCHG8B(Mem) =>
00938         sprintf (str,  "CMPXCHG8B", DIS_MEM);
00939 
00940     | CMPXCHG.Ev.Gvod(Eaddr, reg) =>
00941         sprintf (str,  "CMPXCHG.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00942 
00943     | CMPXCHG.Ev.Gvow(Eaddr, reg) =>
00944         sprintf (str,  "CMPXCHG.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00945 
00946     | CMPXCHG.Eb.Gb(Eaddr, reg) =>
00947         sprintf (str,  "CMPXCHG.Eb.Gb", DIS_EADDR8, DIS_REG8);
00948 
00949     | CMPSvod() =>
00950         sprintf (str,  "CMPSvod");
00951 
00952     | CMPSvow() =>
00953         sprintf (str,  "CMPSvow");
00954 
00955     | CMPSB() =>
00956         sprintf (str,  "CMPSB");
00957 
00958     | CMC() =>
00959         sprintf (str,  "CMC");
00960 
00961     | CLTS() =>
00962         sprintf (str,  "CLTS");
00963 
00964     | CLI() =>
00965         sprintf (str,  "CLI");
00966 
00967     | CLD() =>
00968         sprintf (str,  "CLD");
00969 
00970     | CLC() =>
00971         sprintf (str,  "CLC");
00972 
00973     | CWDE() =>
00974         sprintf (str,  "CWDE");
00975 
00976     | CBW() =>
00977         sprintf (str,  "CBW");
00978 
00979     /* Decode the following as a NOP. We see these in startup code, and anywhere
00980         that calls the OS (as lcall 7, 0) */
00981     | CALL.aPod(seg, off) =>
00982         unused(seg); unused(off);
00983         sprintf (str, "NOP");
00984 
00985     | CALL.Jvod(relocd)  =>
00986         sprintf (str,  name, dis_Num(relocd-hostPC-5));
00987 
00988     | CALL.Evod(Eaddr) =>
00989         sprintf (str,  "CALL.Evod", DIS_EADDR32);
00990 
00991     | BTSiod(Eaddr, i8) =>
00992         sprintf (str,  "BTSiod", DIS_I8, DIS_EADDR32);
00993 
00994     | BTSiow(Eaddr, i8) =>
00995         sprintf (str,  "BTSiow", DIS_I8, DIS_EADDR16);
00996 
00997     | BTSod(Eaddr, reg) =>
00998         sprintf (str,  "BTSod", DIS_EADDR32, DIS_REG32);
00999 
01000     | BTSow(Eaddr, reg) =>
01001         sprintf (str,  "BTSow", DIS_EADDR16, DIS_REG16);
01002 
01003     | BTRiod(Eaddr, i8) =>
01004         sprintf (str,  "BTRiod", DIS_EADDR32, DIS_I8);
01005 
01006     | BTRiow(Eaddr, i8) =>
01007         sprintf (str,  "BTRiow", DIS_EADDR16, DIS_I8);
01008 
01009     | BTRod(Eaddr, reg) =>
01010         sprintf (str,  "BTRod", DIS_EADDR32, DIS_REG32);
01011 
01012     | BTRow(Eaddr, reg) =>
01013         sprintf (str,  "BTRow", DIS_EADDR16, DIS_REG16);
01014 
01015     | BTCiod(Eaddr, i8) =>
01016         sprintf (str,  "BTCiod", DIS_EADDR32, DIS_I8);
01017 
01018     | BTCiow(Eaddr, i8) =>
01019         sprintf (str,  "BTCiow", DIS_EADDR16, DIS_I8);
01020 
01021     | BTCod(Eaddr, reg) =>
01022         sprintf (str,  "BTCod", DIS_EADDR32, DIS_REG32);
01023 
01024     | BTCow(Eaddr, reg) =>
01025         sprintf (str,  "BTCow", DIS_EADDR16, DIS_REG16);
01026 
01027     | BTiod(Eaddr, i8) =>
01028         sprintf (str,  "BTiod", DIS_EADDR32, DIS_I8);
01029 
01030     | BTiow(Eaddr, i8) =>
01031         sprintf (str,  "BTiow", DIS_EADDR16, DIS_I8);
01032 
01033     | BTod(Eaddr, reg) =>
01034         sprintf (str,  "BTod", DIS_EADDR32, DIS_REG32);
01035 
01036     | BTow(Eaddr, reg) =>
01037         sprintf (str,  "BTow", DIS_EADDR16, DIS_REG16);
01038 
01039     | BSWAP(r32) =>
01040         sprintf (str,  "BSWAP", DIS_R32);
01041 
01042     | BSRod(reg, Eaddr) =>
01043         sprintf (str,  "BSRod", DIS_REG32, DIS_EADDR32);
01044 
01045     | BSRow(reg, Eaddr) =>
01046         sprintf (str,  "BSRow", DIS_REG16, DIS_EADDR16);
01047 
01048     | BSFod(reg, Eaddr) =>
01049         sprintf (str,  "BSFod", DIS_REG32, DIS_EADDR32);
01050 
01051     | BSFow(reg, Eaddr) =>
01052         sprintf (str,  "BSFow", DIS_REG16, DIS_EADDR16);
01053 
01054     // Not "user" instructions:
01055 //  | BOUNDod(reg, Mem) =>
01056 //      sprintf (str,  "BOUNDod", DIS_REG32, DIS_MEM);
01057 
01058 //  | BOUNDow(reg, Mem) =>
01059 //      sprintf (str,  "BOUNDow", DIS_REG16, DIS_MEM);
01060 
01061 //    | ARPL(Eaddr, reg ) =>
01062 //        unused(Eaddr); unused(reg);
01063 //        sprintf (str,  "UNIMP");
01064 
01065 //    | AAS() =>
01066 //        sprintf (str,  "AAS");
01067 
01068 //    | AAM() =>
01069 //        sprintf (str,  "AAM");
01070 
01071 //    | AAD() =>
01072 //        sprintf (str,  "AAD");
01073 
01074 //    | AAA() =>
01075 //        sprintf (str,  "AAA");
01076 
01077     | CMPrmod(reg, Eaddr) =>
01078         sprintf (str,  "CMPrmod", DIS_REG32, DIS_EADDR32);
01079 
01080     | CMPrmow(reg, Eaddr) =>
01081         sprintf (str,  "CMPrmow", DIS_REG16, DIS_EADDR16);
01082 
01083     | XORrmod(reg, Eaddr) =>
01084         sprintf (str,  "XORrmod", DIS_REG32, DIS_EADDR32);
01085 
01086     | XORrmow(reg, Eaddr) =>
01087         sprintf (str,  "XORrmow", DIS_REG16, DIS_EADDR16);
01088 
01089     | SUBrmod(reg, Eaddr) =>
01090         sprintf (str,  "SUBrmod", DIS_REG32, DIS_EADDR32);
01091 
01092     | SUBrmow(reg, Eaddr) =>
01093         sprintf (str,  "SUBrmow", DIS_REG16, DIS_EADDR16);
01094 
01095     | ANDrmod(reg, Eaddr) =>
01096         sprintf (str,  "ANDrmod", DIS_REG32, DIS_EADDR32);
01097 
01098     | ANDrmow(reg, Eaddr) =>
01099         sprintf (str,  "ANDrmow", DIS_REG16, DIS_EADDR16);
01100 
01101     | SBBrmod(reg, Eaddr) =>
01102         sprintf (str,  "SBBrmod", DIS_REG32, DIS_EADDR32);
01103 
01104     | SBBrmow(reg, Eaddr) =>
01105         sprintf (str,  "SBBrmow", DIS_REG16, DIS_EADDR16);
01106 
01107     | ADCrmod(reg, Eaddr) =>
01108         sprintf (str,  "ADCrmod", DIS_REG32, DIS_EADDR32);
01109 
01110     | ADCrmow(reg, Eaddr) =>
01111         sprintf (str,  "ADCrmow", DIS_REG16, DIS_EADDR16);
01112 
01113     | ORrmod(reg, Eaddr) =>
01114         sprintf (str,  "ORrmod", DIS_REG32, DIS_EADDR32);
01115 
01116     | ORrmow(reg, Eaddr) =>
01117         sprintf (str,  "ORrmow", DIS_REG16, DIS_EADDR16);
01118 
01119     | ADDrmod(reg, Eaddr) =>
01120         sprintf (str,  "ADDrmod", DIS_REG32, DIS_EADDR32);
01121 
01122     | ADDrmow(reg, Eaddr) =>
01123         sprintf (str,  "ADDrmow", DIS_REG16, DIS_EADDR16);
01124 
01125     | CMPrmb(r8, Eaddr) =>
01126         sprintf (str,  "CMPrmb", DIS_R8, DIS_EADDR8);
01127 
01128     | XORrmb(r8, Eaddr) =>
01129         sprintf (str,  "XORrmb", DIS_R8, DIS_EADDR8);
01130 
01131     | SUBrmb(r8, Eaddr) =>
01132         sprintf (str,  "SUBrmb", DIS_R8, DIS_EADDR8);
01133 
01134     | ANDrmb(r8, Eaddr) =>
01135         sprintf (str,  "ANDrmb", DIS_R8, DIS_EADDR8);
01136 
01137     | SBBrmb(r8, Eaddr) =>
01138         sprintf (str,  "SBBrmb", DIS_R8, DIS_EADDR8);
01139 
01140     | ADCrmb(r8, Eaddr) =>
01141         sprintf (str,  "ADCrmb", DIS_R8, DIS_EADDR8);
01142 
01143     | ORrmb(r8, Eaddr) =>
01144         sprintf (str,  "ORrmb", DIS_R8, DIS_EADDR8);
01145 
01146     | ADDrmb(r8, Eaddr) =>
01147         sprintf (str,  "ADDrmb", DIS_R8, DIS_EADDR8);
01148 
01149     | CMPmrod(Eaddr, reg) =>
01150         sprintf (str,  "CMPmrod", DIS_EADDR32, DIS_REG32);
01151 
01152     | CMPmrow(Eaddr, reg) =>
01153         sprintf (str,  "CMPmrow", DIS_EADDR16, DIS_REG16);
01154 
01155     | XORmrod(Eaddr, reg) =>
01156         sprintf (str,  "XORmrod", DIS_EADDR32, DIS_REG32);
01157 
01158     | XORmrow(Eaddr, reg) =>
01159         sprintf (str,  "XORmrow", DIS_EADDR16, DIS_REG16);
01160 
01161     | SUBmrod(Eaddr, reg) =>
01162         sprintf (str,  "SUBmrod", DIS_EADDR32, DIS_REG32);
01163 
01164     | SUBmrow(Eaddr, reg) =>
01165         sprintf (str,  "SUBmrow", DIS_EADDR16, DIS_REG16);
01166 
01167     | ANDmrod(Eaddr, reg) =>
01168         sprintf (str,  "ANDmrod", DIS_EADDR32, DIS_REG32);
01169 
01170     | ANDmrow(Eaddr, reg) =>
01171         sprintf (str,  "ANDmrow", DIS_EADDR16, DIS_REG16);
01172 
01173     | SBBmrod(Eaddr, reg) =>
01174         sprintf (str,  "SBBmrod", DIS_EADDR32, DIS_REG32);
01175 
01176     | SBBmrow(Eaddr, reg) =>
01177         sprintf (str,  "SBBmrow", DIS_EADDR16, DIS_REG16);
01178 
01179     | ADCmrod(Eaddr, reg) =>
01180         sprintf (str,  "ADCmrod", DIS_EADDR32, DIS_REG32);
01181 
01182     | ADCmrow(Eaddr, reg) =>
01183         sprintf (str,  "ADCmrow", DIS_EADDR16, DIS_REG16);
01184 
01185     | ORmrod(Eaddr, reg) =>
01186         sprintf (str,  "ORmrod", DIS_EADDR32, DIS_REG32);
01187 
01188     | ORmrow(Eaddr, reg) =>
01189         sprintf (str,  "ORmrow", DIS_EADDR16, DIS_REG16);
01190 
01191     | ADDmrod(Eaddr, reg) =>
01192         sprintf (str,  "ADDmrod", DIS_EADDR32, DIS_REG32);
01193 
01194     | ADDmrow(Eaddr, reg) =>
01195         sprintf (str,  "ADDmrow", DIS_EADDR16, DIS_REG16);
01196 
01197     | CMPmrb(Eaddr, r8) =>
01198         sprintf (str,  "CMPmrb", DIS_EADDR8, DIS_R8);
01199 
01200     | XORmrb(Eaddr, r8) =>
01201         sprintf (str,  "XORmrb", DIS_EADDR8, DIS_R8);
01202 
01203     | SUBmrb(Eaddr, r8) =>
01204         sprintf (str,  "SUBmrb", DIS_EADDR8, DIS_R8);
01205 
01206     | ANDmrb(Eaddr, r8) =>
01207         sprintf (str,  "ANDmrb", DIS_EADDR8, DIS_R8);
01208 
01209     | SBBmrb(Eaddr, r8) =>
01210         sprintf (str,  "SBBmrb", DIS_EADDR8, DIS_R8);
01211 
01212     | ADCmrb(Eaddr, r8) =>
01213         sprintf (str,  "ADCmrb", DIS_EADDR8, DIS_R8);
01214 
01215     | ORmrb(Eaddr, r8) =>
01216         sprintf (str,  "ORmrb", DIS_EADDR8, DIS_R8);
01217 
01218     | ADDmrb(Eaddr, r8) =>
01219         sprintf (str,  "ADDmrb", DIS_EADDR8, DIS_R8);
01220 
01221     | CMPiodb(Eaddr, i8) =>
01222         sprintf (str,  "CMPiodb", DIS_EADDR32, DIS_I8);
01223 
01224     | CMPiowb(Eaddr, i8) =>
01225         sprintf (str,  "CMPiowb", DIS_EADDR16, DIS_I8);
01226 
01227     | XORiodb(Eaddr, i8) =>
01228         sprintf (str,  "XORiodb", DIS_EADDR8, DIS_I8);
01229 
01230     | XORiowb(Eaddr, i8) =>
01231         sprintf (str,  "XORiowb", DIS_EADDR16, DIS_I8);
01232 
01233     | SUBiodb(Eaddr, i8) =>
01234         sprintf (str,  "SUBiodb", DIS_EADDR32, DIS_I8);
01235 
01236     | SUBiowb(Eaddr, i8) =>
01237         sprintf (str,  "SUBiowb", DIS_EADDR16, DIS_I8);
01238 
01239     | ANDiodb(Eaddr, i8) =>
01240         sprintf (str,  "ANDiodb", DIS_EADDR8, DIS_I8);
01241 
01242     | ANDiowb(Eaddr, i8) =>
01243         sprintf (str,  "ANDiowb", DIS_EADDR16, DIS_I8);
01244 
01245     | SBBiodb(Eaddr, i8) =>
01246         sprintf (str,  "SBBiodb", DIS_EADDR32, DIS_I8);
01247 
01248     | SBBiowb(Eaddr, i8) =>
01249         sprintf (str,  "SBBiowb", DIS_EADDR16, DIS_I8);
01250 
01251     | ADCiodb(Eaddr, i8) =>
01252         sprintf (str,  "ADCiodb", DIS_EADDR8, DIS_I8);
01253 
01254     | ADCiowb(Eaddr, i8) =>
01255         sprintf (str,  "ADCiowb", DIS_EADDR16, DIS_I8);
01256 
01257     | ORiodb(Eaddr, i8) =>
01258         sprintf (str,  "ORiodb", DIS_EADDR8, DIS_I8);
01259 
01260     | ORiowb(Eaddr, i8) =>
01261         sprintf (str,  "ORiowb", DIS_EADDR16, DIS_I8);
01262 
01263     | ADDiodb(Eaddr, i8) =>
01264         sprintf (str,  "ADDiodb", DIS_EADDR32, DIS_I8);
01265 
01266     | ADDiowb(Eaddr, i8) =>
01267         sprintf (str,  "ADDiowb", DIS_EADDR16, DIS_I8);
01268 
01269     | CMPid(Eaddr, i32) =>
01270         sprintf (str,  "CMPid", DIS_EADDR32, DIS_I32);
01271 
01272     | XORid(Eaddr, i32) =>
01273         sprintf (str,  "XORid", DIS_EADDR32, DIS_I32);
01274 
01275     | SUBid(Eaddr, i32) =>
01276         sprintf (str,  "SUBid", DIS_EADDR32, DIS_I32);
01277 
01278     | ANDid(Eaddr, i32) =>
01279         sprintf (str,  "ANDid", DIS_EADDR32, DIS_I32);
01280 
01281     | SBBid(Eaddr, i32) =>
01282         sprintf (str,  "SBBid", DIS_EADDR32, DIS_I32);
01283 
01284     | ADCid(Eaddr, i32) =>
01285         sprintf (str,  "ADCid", DIS_EADDR32, DIS_I32);
01286 
01287     | ORid(Eaddr, i32) =>
01288         sprintf (str,  "ORid", DIS_EADDR32, DIS_I32);
01289 
01290     | ADDid(Eaddr, i32) =>
01291         sprintf (str,  "ADDid", DIS_EADDR32, DIS_I32);
01292 
01293     | CMPiw(Eaddr, i16) =>
01294         sprintf (str,  "CMPiw", DIS_EADDR16, DIS_I16);
01295 
01296     | XORiw(Eaddr, i16) =>
01297         sprintf (str,  "XORiw", DIS_EADDR16, DIS_I16);
01298 
01299     | SUBiw(Eaddr, i16) =>
01300         sprintf (str,  "SUBiw", DIS_EADDR16, DIS_I16);
01301 
01302     | ANDiw(Eaddr, i16) =>
01303         sprintf (str,  "ANDiw", DIS_EADDR16, DIS_I16);
01304 
01305     | SBBiw(Eaddr, i16) =>
01306         sprintf (str,  "SBBiw", DIS_EADDR16, DIS_I16);
01307 
01308     | ADCiw(Eaddr, i16) =>
01309         sprintf (str,  "ADCiw", DIS_EADDR16, DIS_I16);
01310 
01311     | ORiw(Eaddr, i16) =>
01312         sprintf (str,  "ORiw", DIS_EADDR16, DIS_I16);
01313 
01314     | ADDiw(Eaddr, i16) =>
01315         sprintf (str,  "ADDiw", DIS_EADDR16, DIS_I16);
01316 
01317     | CMPib(Eaddr, i8) =>
01318         sprintf (str,  "CMPib", DIS_EADDR8, DIS_I8);
01319 
01320     | XORib(Eaddr, i8) =>
01321         sprintf (str,  "XORib", DIS_EADDR8, DIS_I8);
01322 
01323     | SUBib(Eaddr, i8) =>
01324         sprintf (str,  "SUBib", DIS_EADDR8, DIS_I8);
01325 
01326     | ANDib(Eaddr, i8) =>
01327         sprintf (str,  "ANDib", DIS_EADDR8, DIS_I8);
01328 
01329     | SBBib(Eaddr, i8) =>
01330         sprintf (str,  "SBBib", DIS_EADDR8, DIS_I8);
01331 
01332     | ADCib(Eaddr, i8) =>
01333         sprintf (str,  "ADCib", DIS_EADDR8, DIS_I8);
01334 
01335     | ORib(Eaddr, i8) =>
01336         sprintf (str,  "ORib", DIS_EADDR8, DIS_I8);
01337 
01338     | ADDib(Eaddr, i8) =>
01339         sprintf (str,  "ADDib", DIS_EADDR8, DIS_I8);
01340 
01341     | CMPiEAX(i32) =>
01342         sprintf (str,  "CMPiEAX", DIS_I32);
01343 
01344     | XORiEAX(i32) =>
01345         sprintf (str,  "XORiEAX", DIS_I32);
01346 
01347     | SUBiEAX(i32) =>
01348         sprintf (str,  "SUBiEAX", DIS_I32);
01349 
01350     | ANDiEAX(i32) =>
01351         sprintf (str,  "ANDiEAX", DIS_I32);
01352 
01353     | SBBiEAX(i32) =>
01354         sprintf (str,  "SBBiEAX", DIS_I32);
01355 
01356     | ADCiEAX(i32) =>
01357         sprintf (str,  "ADCiEAX", DIS_I32);
01358 
01359     | ORiEAX(i32) =>
01360         sprintf (str,  "ORiEAX", DIS_I32);
01361 
01362     | ADDiEAX(i32) =>
01363         sprintf (str,  "ADDiEAX", DIS_I32);
01364 
01365     | CMPiAX(i16) =>
01366         sprintf (str,  "CMPiAX", DIS_I16);
01367 
01368     | XORiAX(i16) =>
01369         sprintf (str,  "XORiAX", DIS_I16);
01370 
01371     | SUBiAX(i16) =>
01372         sprintf (str,  "SUBiAX", DIS_I16);
01373 
01374     | ANDiAX(i16) =>
01375         sprintf (str,  "ANDiAX", DIS_I16);
01376 
01377     | SBBiAX(i16) =>
01378         sprintf (str,  "SBBiAX", DIS_I16);
01379 
01380     | ADCiAX(i16) =>
01381         sprintf (str,  "ADCiAX", DIS_I16);
01382 
01383     | ORiAX(i16) =>
01384         sprintf (str,  "ORiAX", DIS_I16);
01385 
01386     | ADDiAX(i16) =>
01387         sprintf (str,  "ADDiAX", DIS_I16);
01388 
01389     | CMPiAL(i8) =>
01390         sprintf (str,  "CMPiAL", DIS_I8);
01391 
01392     | XORiAL(i8) =>
01393         sprintf (str,  "XORiAL", DIS_I8);
01394 
01395     | SUBiAL(i8) =>
01396         sprintf (str,  "SUBiAL", DIS_I8);
01397 
01398     | ANDiAL(i8) =>
01399         sprintf (str,  "ANDiAL", DIS_I8);
01400 
01401     | SBBiAL(i8) =>
01402         sprintf (str,  "SBBiAL", DIS_I8);
01403 
01404     | ADCiAL(i8) =>
01405         sprintf (str,  "ADCiAL", DIS_I8);
01406 
01407     | ORiAL(i8) =>
01408         sprintf (str,  "ORiAL", DIS_I8);
01409 
01410     | ADDiAL(i8) =>
01411         sprintf (str,  "ADDiAL", DIS_I8);
01412 
01413     | LODSvod() =>
01414         sprintf (str,  "LODSvod");
01415 
01416     | LODSvow() =>
01417         sprintf (str,  "LODSvow");
01418 
01419     | LODSB() =>
01420         sprintf (str,  "LODSB");
01421 
01422     /* Floating point instructions */
01423     | F2XM1() =>
01424         sprintf (str,  "F2XM1");
01425 
01426     | FABS() =>
01427         sprintf (str,  "FABS");
01428 
01429     | FADD.R32(Mem32) =>
01430         sprintf (str,  "FADD.R32", DIS_MEM32);
01431 
01432     | FADD.R64(Mem64) =>
01433         sprintf (str,  "FADD.R64", DIS_MEM64);
01434 
01435     | FADD.ST.STi(idx) =>
01436         sprintf (str,  "FADD.St.STi", DIS_IDX);
01437 
01438     | FADD.STi.ST(idx) =>
01439         sprintf (str,  "FADD.STi.ST", DIS_IDX);
01440 
01441     | FADDP.STi.ST(idx) =>
01442         sprintf (str,  "FADDP.STi.ST", DIS_IDX);
01443 
01444     | FIADD.I32(Mem32) =>
01445         sprintf (str,  "FIADD.I32", DIS_MEM32);
01446 
01447     | FIADD.I16(Mem16) =>
01448         sprintf (str,  "FIADD.I16", DIS_MEM16);
01449 
01450     | FBLD(Mem80) =>
01451         sprintf (str,  "FBLD", DIS_MEM80);
01452 
01453     | FBSTP(Mem80) =>
01454         sprintf (str,  "FBSTP", DIS_MEM80);
01455 
01456     | FCHS() =>
01457         sprintf (str,  "FCHS");
01458 
01459     | FNCLEX() =>
01460         sprintf (str,  "FNCLEX");
01461 
01462     | FCOM.R32(Mem32) =>
01463         sprintf (str,  "FCOM.R32", DIS_MEM32);
01464 
01465     | FCOM.R64(Mem64) =>
01466         sprintf (str,  "FCOM.R64", DIS_MEM64);
01467 
01468     | FICOM.I32(Mem32) =>
01469         sprintf (str,  "FICOM.I32", DIS_MEM32);
01470 
01471     | FICOM.I16(Mem16) =>
01472         sprintf (str,  "FICOM.I16", DIS_MEM16);
01473 
01474     | FCOMP.R32(Mem32) =>
01475         sprintf (str,  "FCOMP.R32", DIS_MEM32);
01476 
01477     | FCOMP.R64(Mem64) =>
01478         sprintf (str,  "FCOMP.R64", DIS_MEM64);
01479 
01480     | FCOM.ST.STi(idx) =>
01481         sprintf (str,  "FCOM.ST.STi", DIS_IDX);
01482 
01483     | FCOMP.ST.STi(idx) =>
01484         sprintf (str,  "FCOMP.ST.STi", DIS_IDX);
01485 
01486     | FICOMP.I32(Mem32) =>
01487         sprintf (str,  "FICOMP.I32", DIS_MEM32);
01488 
01489     | FICOMP.I16(Mem16) =>
01490         sprintf (str,  "FICOMP.I16", DIS_MEM16);
01491 
01492     | FCOMPP() =>
01493         sprintf (str,  "FCOMPP");
01494 
01495     | FCOMI.ST.STi(idx)  =>
01496         sprintf (str, name, DIS_IDX);
01497 
01498     | FCOMIP.ST.STi(idx)  =>
01499         sprintf (str, name, DIS_IDX);
01500 
01501     | FCOS() =>
01502         sprintf (str,  "FCOS");
01503 
01504     | FDECSTP() =>
01505         sprintf (str,  "FDECSTP");
01506 
01507     | FDIV.R32(Mem32) =>
01508         sprintf (str,  "FDIV.R32", DIS_MEM32);
01509 
01510     | FDIV.R64(Mem64) =>
01511         sprintf (str,  "FDIV.R64", DIS_MEM64);
01512 
01513     | FDIV.ST.STi(idx) =>
01514         sprintf (str,  "FDIV.ST.STi", DIS_IDX);
01515 
01516     | FDIV.STi.ST(idx) =>
01517         sprintf (str,  "FDIV.STi.ST", DIS_IDX);
01518 
01519     | FDIVP.STi.ST(idx) =>
01520         sprintf (str,  "FDIVP.STi.ST", DIS_IDX);
01521 
01522     | FIDIV.I32(Mem32) =>
01523         sprintf (str,  "FIDIV.I32", DIS_MEM32);
01524 
01525     | FIDIV.I16(Mem16) =>
01526         sprintf (str,  "FIDIV.I16", DIS_MEM16);
01527 
01528     | FDIVR.R32(Mem32) =>
01529         sprintf (str,  "FDIVR.R32", DIS_MEM32);
01530 
01531     | FDIVR.R64(Mem64) =>
01532         sprintf (str,  "FDIVR.R64", DIS_MEM64);
01533 
01534     | FDIVR.ST.STi(idx) =>
01535         sprintf (str,  "FDIVR.ST.STi", DIS_IDX);
01536 
01537     | FDIVR.STi.ST(idx) =>
01538         sprintf (str,  "FDIVR.STi.ST", DIS_IDX);
01539 
01540     | FIDIVR.I32(Mem32) =>
01541         sprintf (str,  "FIDIVR.I32", DIS_MEM32);
01542 
01543     | FIDIVR.I16(Mem16) =>
01544         sprintf (str,  "FIDIVR.I16", DIS_MEM16);
01545 
01546     | FDIVRP.STi.ST(idx) =>
01547         sprintf (str,  "FDIVRP.STi.ST", DIS_IDX);
01548 
01549     | FFREE(idx) =>
01550         sprintf (str,  "FFREE", DIS_IDX);
01551 
01552     | FILD.lsI16(Mem16) =>
01553         sprintf (str,  "FILD.lsI16", DIS_MEM16);
01554 
01555     | FILD.lsI32(Mem32) =>
01556         sprintf (str,  "FILD.lsI32", DIS_MEM32);
01557 
01558     | FILD64(Mem64) =>
01559         sprintf (str,  "FILD64", DIS_MEM64);
01560 
01561     | FINIT() =>
01562         sprintf (str,  "FINIT");
01563 
01564     | FIST.lsI16(Mem16) =>
01565         sprintf (str,  "FIST.lsI16", DIS_MEM16);
01566 
01567     | FIST.lsI32(Mem32) =>
01568         sprintf (str,  "FIST.lsI32", DIS_MEM32);
01569 
01570     | FISTP.lsI16(Mem16) =>
01571         sprintf (str,  "FISTP.lsI16", DIS_MEM16);
01572 
01573     | FISTP.lsI32(Mem32) =>
01574         sprintf (str,  "FISTP.lsI32", DIS_MEM32);
01575 
01576     | FISTP64(Mem64) =>
01577         sprintf (str,  "FISTP64", DIS_MEM64);
01578 
01579     | FLD.lsR32(Mem32) =>
01580         sprintf (str,  "FLD.lsR32", DIS_MEM32);
01581 
01582     | FLD.lsR64(Mem64) =>
01583         sprintf (str,  "FLD.lsR64", DIS_MEM64);
01584 
01585     | FLD80(Mem80) =>
01586         sprintf (str,  "FLD80", DIS_MEM80);
01587 
01588 /* This is a bit tricky. The FPUSH logically comes between the read of STi and
01589 # the write to ST0. In particular, FLD ST0 is supposed to duplicate the TOS.
01590 # This problem only happens with this load instruction, so there is a work
01591 # around here that gives us the SSL a value of i that is one more than in
01592 # the instruction */
01593     | FLD.STi(idx) =>
01594         sprintf (str,  "FLD.STi", DIS_IDXP1);
01595 
01596     | FLD1() =>
01597         sprintf (str,  "FLD1");
01598 
01599     | FLDL2T() =>
01600         sprintf (str,  "FLDL2T");
01601 
01602     | FLDL2E() =>
01603         sprintf (str,  "FLDL2E");
01604 
01605     | FLDPI() =>
01606         sprintf (str,  "FLDPI");
01607 
01608     | FLDLG2() =>
01609         sprintf (str,  "FLDLG2");
01610 
01611     | FLDLN2() =>
01612         sprintf (str,  "FLDLN2");
01613 
01614     | FLDZ() =>
01615         sprintf (str,  "FLDZ");
01616 
01617     | FLDCW(Mem16) =>
01618         sprintf (str,  "FLDCW", DIS_MEM16);
01619 
01620     | FLDENV(Mem) =>
01621         sprintf (str,  "FLDENV", DIS_MEM);
01622 
01623     | FMUL.R32(Mem32) =>
01624         sprintf (str,  "FMUL.R32", DIS_MEM32);
01625 
01626     | FMUL.R64(Mem64) =>
01627         sprintf (str,  "FMUL.R64", DIS_MEM64);
01628 
01629     | FMUL.ST.STi(idx) =>
01630         sprintf (str,  "FMUL.ST.STi", DIS_IDX);
01631 
01632     | FMUL.STi.ST(idx) =>
01633         sprintf (str,  "FMUL.STi.ST", DIS_IDX);
01634 
01635     | FMULP.STi.ST(idx) =>
01636         sprintf (str,  "FMULP.STi.ST", DIS_IDX);
01637 
01638     | FIMUL.I32(Mem32) =>
01639         sprintf (str,  "FIMUL.I32", DIS_MEM32);
01640 
01641     | FIMUL.I16(Mem16) =>
01642         sprintf (str,  "FIMUL.I16", DIS_MEM16);
01643 
01644     | FNOP() =>
01645         sprintf (str,  "FNOP");
01646 
01647     | FPATAN() =>
01648         sprintf (str,  "FPATAN");
01649 
01650     | FPREM() =>
01651         sprintf (str,  "FPREM");
01652 
01653     | FPREM1() =>
01654         sprintf (str,  "FPREM1");
01655 
01656     | FPTAN() =>
01657         sprintf (str,  "FPTAN");
01658 
01659     | FRNDINT() =>
01660         sprintf (str,  "FRNDINT");
01661 
01662     | FRSTOR(Mem) =>
01663         sprintf (str,  "FRSTOR", DIS_MEM);
01664 
01665     | FNSAVE(Mem) =>
01666         sprintf (str,  "FNSAVE", DIS_MEM);
01667 
01668     | FSCALE() =>
01669         sprintf (str,  "FSCALE");
01670 
01671     | FSIN() =>
01672         sprintf (str,  "FSIN");
01673 
01674     | FSINCOS() =>
01675         sprintf (str,  "FSINCOS");
01676 
01677     | FSQRT() =>
01678         sprintf (str,  "FSQRT");
01679 
01680     | FST.lsR32(Mem32) =>
01681         sprintf (str,  "FST.lsR32", DIS_MEM32);
01682 
01683     | FST.lsR64(Mem64) =>
01684         sprintf (str,  "FST.lsR64", DIS_MEM64);
01685 
01686     | FSTP.lsR32(Mem32) =>
01687         sprintf (str,  "FSTP.lsR32", DIS_MEM32);
01688 
01689     | FSTP.lsR64(Mem64) =>
01690         sprintf (str,  "FSTP.lsR64", DIS_MEM64);
01691 
01692     | FSTP80(Mem80) =>
01693         sprintf (str,  "FSTP80", DIS_MEM80);
01694 
01695     | FST.st.STi(idx) =>
01696         sprintf (str,  "FST.st.STi", DIS_IDX);
01697 
01698     | FSTP.st.STi(idx) =>
01699         sprintf (str,  "FSTP.st.STi", DIS_IDX);
01700 
01701     | FSTCW(Mem16) =>
01702         sprintf (str,  "FSTCW", DIS_MEM16);
01703 
01704     | FSTENV(Mem) =>
01705         sprintf (str,  "FSTENV", DIS_MEM);
01706 
01707     | FSTSW(Mem16) =>
01708         sprintf (str,  "FSTSW", DIS_MEM16);
01709 
01710     | FSTSW.AX() =>
01711         sprintf (str,  "FSTSW.AX");
01712 
01713     | FSUB.R32(Mem32) =>
01714         sprintf (str,  "FSUB.R32", DIS_MEM32);
01715 
01716     | FSUB.R64(Mem64) =>
01717         sprintf (str,  "FSUB.R64", DIS_MEM64);
01718 
01719     | FSUB.ST.STi(idx) =>
01720         sprintf (str,  "FSUB.ST.STi", DIS_IDX);
01721 
01722     | FSUB.STi.ST(idx) =>
01723         sprintf (str,  "FSUB.STi.ST", DIS_IDX);
01724 
01725     | FISUB.I32(Mem32) =>
01726         sprintf (str,  "FISUB.I32", DIS_MEM32);
01727 
01728     | FISUB.I16(Mem16) =>
01729         sprintf (str,  "FISUB.I16", DIS_MEM16);
01730 
01731     | FSUBP.STi.ST(idx) =>
01732         sprintf (str,  "FSUBP.STi.ST", DIS_IDX);
01733 
01734     | FSUBR.R32(Mem32) =>
01735         sprintf (str,  "FSUBR.R32", DIS_MEM32);
01736 
01737     | FSUBR.R64(Mem64) =>
01738         sprintf (str,  "FSUBR.R64", DIS_MEM64);
01739 
01740     | FSUBR.ST.STi(idx) =>
01741         sprintf (str,  "FSUBR.ST.STi", DIS_IDX);
01742 
01743     | FSUBR.STi.ST(idx) =>
01744         sprintf (str,  "FSUBR.STi.ST", DIS_IDX);
01745 
01746     | FISUBR.I32(Mem32) =>
01747         sprintf (str,  "FISUBR.I32", DIS_MEM32);
01748 
01749     | FISUBR.I16(Mem16) =>
01750         sprintf (str,  "FISUBR.I16", DIS_MEM16);
01751 
01752     | FSUBRP.STi.ST(idx) =>
01753         sprintf (str,  "FSUBRP.STi.ST", DIS_IDX);
01754 
01755     | FTST() =>
01756         sprintf (str,  "FTST");
01757 
01758     | FUCOM(idx) =>
01759         sprintf (str,  "FUCOM", DIS_IDX);
01760 
01761     | FUCOMP(idx) =>
01762         sprintf (str,  "FUCOMP", DIS_IDX);
01763 
01764     | FUCOMPP() =>
01765         sprintf (str,  "FUCOMPP");
01766 
01767     | FUCOMI.ST.STi(idx)  =>
01768         sprintf (str, name, DIS_IDX);
01769 
01770     | FUCOMIP.ST.STi(idx)  =>
01771         sprintf (str, name, DIS_IDX);
01772 
01773     | FXAM() =>
01774         sprintf (str,  "FXAM");
01775 
01776     | FXCH(idx) =>
01777         sprintf (str,  "FXCH", DIS_IDX);
01778 
01779     | FXTRACT() =>
01780         sprintf (str,  "FXTRACT");
01781 
01782     | FYL2X() =>
01783         sprintf (str,  "FYL2X");
01784 
01785     | FYL2XP1() =>
01786         sprintf (str,  "FYL2XP1");
01787 
01788 //  | inst = n =>
01789 //      sprintf (str, "%0x", n);
01790 
01791     else
01792         sprintf (str, "%0x", n);
01793 
01794     endmatch
01795 
01796     // return # of bytes parsed
01797     return (nextPC - hostPC);
01798 }
01799
pentium/disassembler.m
