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pentium/decoder.m

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00001 /*
00002  * Copyright (C) 1998-2001, The University of Queensland
00003  *
00004  * See the file "LICENSE.TERMS" for information on usage and
00005  * redistribution of this file, and for a DISCLAIMER OF ALL
00006  * WARRANTIES.
00007  *
00008  */
00009 
00010 /*==============================================================================
00011  * FILE:       decoder.m
00012  * OVERVIEW:   This file contains the high level decoding functionality, for example matching logues, calls, branches,
00013  *              etc. Ordinary instructions are processed in decoder_low.m
00014  *============================================================================*/ 
00015 /*
00016  * $Revision: 1.39 $    // 1.33.2.2
00017  *
00018  * 26 Apr 02 - Mike: Changes for boomerang
00019  * 18 Nov 02 - Mike: Mods for MOV.Ed.Iv^od etc. Also suppressed warning re name
00020  * 09 Dec 02 - Mike: Changed DIS_REG32 to use dis_Reg again, because in the
00021  *              SSL file we have reg32 instead of r[reg32] (compat with SPARC)
00022  * 07 May 03 - Mike: Fixed several arithmetic and logical "iodb" instructions
00023  *              that had 8 bit instead of 32 bit modrm sizes
00024  * 24 Oct 03 - Mike: Fixed DIS_IDXP1: did not have +32 in macro
00025  * 02 Sep 05 - Mike: POP.Evod/w take Eaddr now, not Mem
00026 */
00027 
00028 #include <assert.h>
00029 #if defined(_MSC_VER) && _MSC_VER <= 1100
00030 #include "signature.h"
00031 #endif
00032 
00033 #include "rtl.h"
00034 #include "decoder.h"
00035 #include "pentiumdecoder.h"
00036 #include "prog.h"
00037 #include "exp.h"
00038 #include "proc.h"
00039 #include "boomerang.h"
00040 #include "statement.h"
00041 
00042 #define DIS_R8    (dis_Reg(r8+8))
00043 #define DIS_R16   (dis_Reg(r16+0))
00044 #define DIS_R32   (dis_Reg(r32+24))
00045 #define DIS_REG8  (dis_Reg(reg+8))
00046 #define DIS_REG16 (dis_Reg(reg+0))
00047 #define DIS_REG32 (dis_Reg(reg+24))
00048 #define DIS_SR16  (dis_Reg(sr16+16))
00049 #define DIS_IDX   (dis_Reg(idx+32))
00050 #define DIS_IDXP1 (dis_Reg((idx+1)%7+32))
00051 
00052 #define DIS_EADDR32 (dis_Eaddr(Eaddr, 32))
00053 #define DIS_EADDR16 (dis_Eaddr(Eaddr, 16))
00054 #define DIS_EADDR8  (dis_Eaddr(Eaddr,  8))
00055 #define DIS_MEM     (dis_Mem(Mem))
00056 #define DIS_MEM16   (dis_Mem(Mem16))    // Probably needs changing
00057 #define DIS_MEM32   (dis_Mem(Mem32))    // Probably needs changing
00058 #define DIS_MEM64   (dis_Mem(Mem64))    // Probably needs changing
00059 #define DIS_MEM80   (dis_Mem(Mem80))    // Probably needs changing
00060 
00061 #define DIS_I32     (addReloc(new Const(i32)))
00062 #define DIS_I16     (new Const(i16))
00063 #define DIS_I8      (new Const(i8))
00064 #define DIS_COUNT   (new Const(count))
00065 #define DIS_OFF     (addReloc(new Const(off)))
00066 
00067 
00068 // Function to generate statements for the BSF/BSR series (Bit Scan Forward/
00069 // Reverse)
00070 void genBSFR(ADDRESS pc, Exp* reg, Exp* modrm, int init, int size, OPER incdec,
00071     int numBytes);
00072 
00073 /**********************************
00074  * PentiumDecoder methods.
00075  **********************************/   
00076 
00077 /*==============================================================================
00078  * FUNCTION:       unused
00079  * OVERVIEW:       A dummy function to suppress "unused local variable" messages
00080  * PARAMETERS:     x: integer variable to be "used"
00081  * RETURNS:        Nothing
00082  *============================================================================*/
00083 void PentiumDecoder::unused(int x)
00084 {}
00085 
00086 /*==============================================================================
00087  * FUNCTION:       PentiumDecoder::decodeInstruction
00088  * OVERVIEW:       Decodes a machine instruction and returns an RTL instance. In most cases a single instruction is
00089  *                  decoded. However, if a higher level construct that may consist of multiple instructions is matched,
00090  *                  then there may be a need to return more than one RTL. The caller_prologue2 is an example of such
00091  *                  a construct which encloses an abritary instruction that must be decoded into its own RTL.
00092  * PARAMETERS:     pc - the native address of the pc
00093  *                 delta - the difference between the above address and the host address of the pc (i.e. the address
00094  *                  that the pc is at in the loaded object file)
00095  *                 RTLDict - the dictionary of RTL templates used to instantiate the RTL for the instruction being
00096  *                  decoded
00097  *                 proc - the enclosing procedure
00098  * RETURNS:        a DecodeResult structure containing all the information gathered during decoding
00099  *============================================================================*/
00100 static DecodeResult result;
00101 DecodeResult& PentiumDecoder::decodeInstruction (ADDRESS pc, int delta)
00102 {
00103     ADDRESS hostPC = pc + delta;
00104 
00105     // Clear the result structure;
00106     result.reset();
00107 
00108     // The actual list of instantiated Statements
00109     std::list<Statement*>* stmts = NULL;
00110 
00111 
00112     ADDRESS nextPC = NO_ADDRESS;
00113     match  hostPC to
00114     
00115     | CALL.Evod(Eaddr) =>
00116         /*
00117          * Register call
00118          */
00119         // Mike: there should probably be a HLNwayCall class for this!
00120         stmts = instantiate(pc,  "CALL.Evod", DIS_EADDR32);
00121         CallStatement* newCall = new CallStatement;
00122         // Record the fact that this is a computed call
00123         newCall->setIsComputed();
00124         // Set the destination expression
00125         newCall->setDest(DIS_EADDR32);
00126         result.rtl = new RTL(pc, stmts);
00127         result.rtl->appendStmt(newCall);
00128         // Only one instruction, so size of result is size of this decode
00129         //result.numBytes = nextPC - hostPC;
00130 
00131     | JMP.Evod(Eaddr) =>
00132         /*
00133          * Register jump
00134          */
00135         CaseStatement* newJump = new CaseStatement;
00136         // Record the fact that this is a computed call
00137         newJump->setIsComputed();
00138         // Set the destination expression
00139         newJump->setDest(DIS_EADDR32);
00140         result.rtl = new RTL(pc, stmts);
00141         result.rtl->appendStmt(newJump);
00142         // Only one instruction, so size of result is size of this decode
00143         //result.numBytes = nextPC - hostPC;
00144     
00145     /*
00146      * Unconditional branches
00147      */
00148     | JMP.Jvod(relocd)  =>
00149         unused((int) name);
00150         unconditionalJump(name, 5, relocd, delta, pc, stmts, result);
00151     | JMP.Jvow(relocd)  =>
00152         unused((int) name);
00153         unconditionalJump(name, 3, relocd, delta, pc, stmts, result);
00154     | JMP.Jb(relocd)  =>
00155         unused((int) name);
00156         unconditionalJump(name, 2, relocd, delta, pc, stmts, result);
00157 
00158     /*
00159      * Conditional branches, 8 bit offset: 7X XX
00160      */
00161     | Jb.NLE(relocd) =>
00162         COND_JUMP("Jb.NLE", 2, relocd, BRANCH_JSG)
00163     | Jb.LE(relocd) =>
00164         COND_JUMP("Jb.LE", 2, relocd, BRANCH_JSLE)
00165     | Jb.NL(relocd) =>
00166         COND_JUMP("Jb.NL", 2, relocd, BRANCH_JSGE)
00167     | Jb.L(relocd) =>
00168         COND_JUMP("Jb.L", 2, relocd, BRANCH_JSL)
00169     | Jb.NP(relocd) =>
00170         COND_JUMP("Jb.NP", 2, relocd, (BRANCH_TYPE)0)
00171     | Jb.P(relocd) =>
00172         COND_JUMP("Jb.P", 2, relocd, BRANCH_JPAR)
00173     | Jb.NS(relocd) =>
00174         COND_JUMP("Jb.NS", 2, relocd, BRANCH_JPOS)
00175     | Jb.S(relocd) =>
00176         COND_JUMP("Jb.S", 2, relocd, BRANCH_JMI)
00177     | Jb.NBE(relocd) =>
00178         COND_JUMP("Jb.NBE", 2, relocd, BRANCH_JUG)
00179     | Jb.BE(relocd) =>
00180         COND_JUMP("Jb.BE", 2, relocd, BRANCH_JULE)
00181     | Jb.NZ(relocd) =>
00182         COND_JUMP("Jb.NZ", 2, relocd, BRANCH_JNE)
00183     | Jb.Z(relocd) =>
00184         COND_JUMP("Jb.Z", 2, relocd, BRANCH_JE)
00185     | Jb.NB(relocd) =>
00186         COND_JUMP("Jb.NB", 2, relocd, BRANCH_JUGE)
00187     | Jb.B(relocd) =>
00188         COND_JUMP("Jb.B", 2, relocd, BRANCH_JUL)
00189     | Jb.NO(relocd) =>
00190         COND_JUMP("Jb.NO", 2, relocd, (BRANCH_TYPE)0)
00191     | Jb.O(relocd) =>
00192         COND_JUMP("Jb.O", 2, relocd, (BRANCH_TYPE)0)
00193 
00194     /*
00195      * Conditional branches, 16 bit offset: 66 0F 8X XX XX
00196      */
00197     | Jv.NLEow(relocd) =>
00198         COND_JUMP("Jv.NLEow", 4, relocd, BRANCH_JSG)
00199     | Jv.LEow(relocd) =>
00200         COND_JUMP("Jv.LEow", 4, relocd, BRANCH_JSLE)
00201     | Jv.NLow(relocd) =>
00202         COND_JUMP("Jv.NLow", 4, relocd, BRANCH_JSGE)
00203     | Jv.Low(relocd) =>
00204         COND_JUMP("Jv.Low", 4, relocd, BRANCH_JSL)
00205     | Jv.NPow(relocd) =>
00206         COND_JUMP("Jv.NPow", 4, relocd, (BRANCH_TYPE)0)
00207     | Jv.Pow(relocd) =>
00208         COND_JUMP("Jv.Pow", 4, relocd, BRANCH_JPAR)
00209     | Jv.NSow(relocd) =>
00210         COND_JUMP("Jv.NSow", 4, relocd, BRANCH_JPOS)
00211     | Jv.Sow(relocd) =>
00212         COND_JUMP("Jv.Sow", 4, relocd, BRANCH_JMI)
00213     | Jv.NBEow(relocd) =>
00214         COND_JUMP("Jv.NBEow", 4, relocd, BRANCH_JUG)
00215     | Jv.BEow(relocd) =>
00216         COND_JUMP("Jv.BEow", 4, relocd, BRANCH_JULE)
00217     | Jv.NZow(relocd) =>
00218         COND_JUMP("Jv.NZow", 4, relocd, BRANCH_JNE)
00219     | Jv.Zow(relocd) =>
00220         COND_JUMP("Jv.Zow", 4, relocd, BRANCH_JE)
00221     | Jv.NBow(relocd) =>
00222         COND_JUMP("Jv.NBow", 4, relocd, BRANCH_JUGE)
00223     | Jv.Bow(relocd) =>
00224         COND_JUMP("Jv.Bow", 4, relocd, BRANCH_JUL)
00225     | Jv.NOow(relocd) =>
00226         COND_JUMP("Jv.NOow", 4, relocd, (BRANCH_TYPE)0)
00227     | Jv.Oow(relocd) =>
00228         COND_JUMP("Jv.Oow", 4, relocd, (BRANCH_TYPE)0)
00229 
00230     /*
00231      * Conditional branches, 32 bit offset: 0F 8X XX XX XX XX
00232      */
00233     | Jv.NLEod(relocd) =>
00234         COND_JUMP("Jv.NLEod", 6, relocd, BRANCH_JSG)
00235     | Jv.LEod(relocd) =>
00236         COND_JUMP("Jv.LEod", 6, relocd, BRANCH_JSLE)
00237     | Jv.NLod(relocd) =>
00238         COND_JUMP("Jv.NLod", 6, relocd, BRANCH_JSGE)
00239     | Jv.Lod(relocd) =>
00240         COND_JUMP("Jv.Lod", 6, relocd, BRANCH_JSL)
00241     | Jv.NPod(relocd) =>
00242         COND_JUMP("Jv.NPod", 6, relocd, (BRANCH_TYPE)0)
00243     | Jv.Pod(relocd) =>
00244         COND_JUMP("Jv.Pod", 6, relocd, BRANCH_JPAR)
00245     | Jv.NSod(relocd) =>
00246         COND_JUMP("Jv.NSod", 6, relocd, BRANCH_JPOS)
00247     | Jv.Sod(relocd) =>
00248         COND_JUMP("Jv.Sod", 6, relocd, BRANCH_JMI)
00249     | Jv.NBEod(relocd) =>
00250         COND_JUMP("Jv.NBEod", 6, relocd, BRANCH_JUG)
00251     | Jv.BEod(relocd) =>
00252         COND_JUMP("Jv.BEod", 6, relocd, BRANCH_JULE)
00253     | Jv.NZod(relocd) =>
00254         COND_JUMP("Jv.NZod", 6, relocd, BRANCH_JNE)
00255     | Jv.Zod(relocd) =>
00256         COND_JUMP("Jv.Zod", 6, relocd, BRANCH_JE)
00257     | Jv.NBod(relocd) =>
00258         COND_JUMP("Jv.NBod", 6, relocd, BRANCH_JUGE)
00259     | Jv.Bod(relocd) =>
00260         COND_JUMP("Jv.Bod", 6, relocd, BRANCH_JUL)
00261     | Jv.NOod(relocd) =>
00262         COND_JUMP("Jv.NOod", 6, relocd, (BRANCH_TYPE)0)
00263     | Jv.Ood(relocd) =>
00264         COND_JUMP("Jv.Ood", 6, relocd, (BRANCH_TYPE)0)
00265 
00266     | SETb.NLE(Eaddr)  =>
00267         stmts = instantiate(pc, name, DIS_EADDR8);
00268         SETS(name, DIS_EADDR8, BRANCH_JSG)
00269     | SETb.LE(Eaddr)  =>
00270         stmts = instantiate(pc, name, DIS_EADDR8);
00271         SETS(name, DIS_EADDR8, BRANCH_JSLE)
00272     | SETb.NL(Eaddr)  =>
00273         stmts = instantiate(pc, name, DIS_EADDR8);
00274         SETS(name, DIS_EADDR8, BRANCH_JSGE)
00275     | SETb.L(Eaddr)  =>
00276         stmts = instantiate(pc, name, DIS_EADDR8);
00277         SETS(name, DIS_EADDR8, BRANCH_JSL)
00278     //| SETb.NP(Eaddr) [name] =>
00279     //  stmts = instantiate(pc, name, DIS_EADDR8);
00280     //  SETS(name, DIS_EADDR8, BRANCH_JSG)
00281     //| SETb.P(Eaddr) [name] =>
00282     //  stmts = instantiate(pc, name, DIS_EADDR8);
00283     //  SETS(name, DIS_EADDR8, BRANCH_JSG)
00284     | SETb.NS(Eaddr)  =>
00285         stmts = instantiate(pc, name, DIS_EADDR8);
00286         SETS(name, DIS_EADDR8, BRANCH_JPOS)
00287     | SETb.S(Eaddr)  =>
00288         stmts = instantiate(pc, name, DIS_EADDR8);
00289         SETS(name, DIS_EADDR8, BRANCH_JMI)
00290     | SETb.NBE(Eaddr)  =>
00291         stmts = instantiate(pc, name, DIS_EADDR8);
00292         SETS(name, DIS_EADDR8, BRANCH_JUG)
00293     | SETb.BE(Eaddr)  =>
00294         stmts = instantiate(pc, name, DIS_EADDR8);
00295         SETS(name, DIS_EADDR8, BRANCH_JULE)
00296     | SETb.NZ(Eaddr)  =>
00297         stmts = instantiate(pc, name, DIS_EADDR8);
00298         SETS(name, DIS_EADDR8, BRANCH_JNE)
00299     | SETb.Z(Eaddr)  =>
00300         stmts = instantiate(pc, name, DIS_EADDR8);
00301         SETS(name, DIS_EADDR8, BRANCH_JE)
00302     | SETb.NB(Eaddr)  =>
00303         stmts = instantiate(pc, name, DIS_EADDR8);
00304         SETS(name, DIS_EADDR8, BRANCH_JUGE)
00305     | SETb.B(Eaddr)  =>
00306         stmts = instantiate(pc, name, DIS_EADDR8);
00307         SETS(name, DIS_EADDR8, BRANCH_JUL)
00308     //| SETb.NO(Eaddr) [name] =>
00309     //  stmts = instantiate(pc, name, DIS_EADDR8);
00310     //  SETS(name, DIS_EADDR8, BRANCH_JSG)
00311     //| SETb.O(Eaddr) [name] =>
00312     //  stmts = instantiate(pc, name, DIS_EADDR8);
00313     //  SETS(name, DIS_EADDR8, BRANCH_JSG)
00314 
00315     | XLATB() =>
00316         stmts = instantiate(pc,  "XLATB");
00317 
00318     | XCHG.Ev.Gvod(Eaddr, reg) =>
00319         stmts = instantiate(pc,  "XCHG.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00320 
00321     | XCHG.Ev.Gvow(Eaddr, reg) =>
00322         stmts = instantiate(pc,  "XCHG.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00323 
00324     | XCHG.Eb.Gb(Eaddr, reg) =>
00325         stmts = instantiate(pc,  "XCHG.Eb.Gb", DIS_EADDR8, DIS_REG8);
00326 
00327     | NOP() =>
00328         stmts = instantiate(pc,  "NOP");
00329 
00330     | SEG.CS() =>        // For now, treat seg.cs as a 1 byte NOP
00331         stmts = instantiate(pc,  "NOP");
00332 
00333     | SEG.DS() =>        // For now, treat seg.ds as a 1 byte NOP
00334         stmts = instantiate(pc,  "NOP");
00335 
00336     | SEG.ES() =>        // For now, treat seg.es as a 1 byte NOP
00337         stmts = instantiate(pc,  "NOP");
00338 
00339     | SEG.FS() =>        // For now, treat seg.fs as a 1 byte NOP
00340         stmts = instantiate(pc,  "NOP");
00341 
00342     | SEG.GS() =>        // For now, treat seg.gs as a 1 byte NOP
00343         stmts = instantiate(pc,  "NOP");
00344 
00345     | SEG.SS() =>        // For now, treat seg.ss as a 1 byte NOP
00346         stmts = instantiate(pc,  "NOP");
00347 
00348     | XCHGeAXod(r32) =>
00349         stmts = instantiate(pc,  "XCHGeAXod", DIS_R32);
00350 
00351     | XCHGeAXow(r32) =>
00352         stmts = instantiate(pc,  "XCHGeAXow", DIS_R32);
00353 
00354     | XADD.Ev.Gvod(Eaddr, reg) =>
00355         stmts = instantiate(pc,  "XADD.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00356 
00357     | XADD.Ev.Gvow(Eaddr, reg) =>
00358         stmts = instantiate(pc,  "XADD.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00359 
00360     | XADD.Eb.Gb(Eaddr, reg) =>
00361         stmts = instantiate(pc,  "XADD.Eb.Gb", DIS_EADDR8, DIS_REG8);
00362 
00363     | WRMSR() =>
00364         stmts = instantiate(pc,  "WRMSR");
00365 
00366     | WBINVD() =>
00367         stmts = instantiate(pc,  "WBINVD");
00368 
00369     | WAIT() =>
00370         stmts = instantiate(pc,  "WAIT");
00371 
00372     | VERW(Eaddr) =>
00373         stmts = instantiate(pc,  "VERW", DIS_EADDR32);
00374 
00375     | VERR(Eaddr) =>
00376         stmts = instantiate(pc,  "VERR", DIS_EADDR32);
00377 
00378     | TEST.Ev.Gvod(Eaddr, reg) =>
00379         stmts = instantiate(pc,  "TEST.Ev.Gvod", DIS_EADDR32, DIS_REG32);
00380 
00381     | TEST.Ev.Gvow(Eaddr, reg) =>
00382         stmts = instantiate(pc,  "TEST.Ev.Gvow", DIS_EADDR16, DIS_REG16);
00383 
00384     | TEST.Eb.Gb(Eaddr, reg) =>
00385         stmts = instantiate(pc,  "TEST.Eb.Gb", DIS_EADDR8, DIS_REG8);
00386 
00387     | TEST.Ed.Id(Eaddr, i32) =>
00388         stmts = instantiate(pc,  "TEST.Ed.Id", DIS_EADDR32, DIS_I32);
00389 
00390     | TEST.Ew.Iw(Eaddr, i16) =>
00391         stmts = instantiate(pc,  "TEST.Ew.Iw", DIS_EADDR16, DIS_I16);
00392 
00393     | TEST.Eb.Ib(Eaddr, i8) =>
00394         stmts = instantiate(pc,  "TEST.Eb.Ib", DIS_EADDR8, DIS_I8);
00395 
00396     | TEST.eAX.Ivod(i32) =>
00397         stmts = instantiate(pc,  "TEST.eAX.Ivod", DIS_I32);
00398 
00399     | TEST.eAX.Ivow(i16) =>
00400         stmts = instantiate(pc,  "TEST.eAX.Ivow", DIS_I16);
00401 
00402     | TEST.AL.Ib(i8) =>
00403         stmts = instantiate(pc,  "TEST.AL.Ib", DIS_I8);
00404 
00405     | STR(Mem) =>
00406         stmts = instantiate(pc,  "STR", DIS_MEM);
00407 
00408     | STOSvod() =>
00409         stmts = instantiate(pc,  "STOSvod");
00410 
00411     | STOSvow() =>
00412         stmts = instantiate(pc,  "STOSvow");
00413 
00414     | STOSB() =>
00415         stmts = instantiate(pc,  "STOSB");
00416 
00417     | STI() =>
00418         stmts = instantiate(pc,  "STI");
00419 
00420     | STD() =>
00421         stmts = instantiate(pc,  "STD");
00422 
00423     | STC() =>
00424         stmts = instantiate(pc,  "STC");
00425 
00426     | SMSW(Eaddr) =>
00427         stmts = instantiate(pc,  "SMSW", DIS_EADDR32);
00428 
00429     | SLDT(Eaddr) =>
00430         stmts = instantiate(pc,  "SLDT", DIS_EADDR32);
00431 
00432     | SHLD.CLod(Eaddr, reg) =>
00433         stmts = instantiate(pc,  "SHLD.CLod", DIS_EADDR32, DIS_REG32);
00434 
00435     | SHLD.CLow(Eaddr, reg) =>
00436         stmts = instantiate(pc,  "SHLD.CLow", DIS_EADDR16, DIS_REG16);
00437 
00438     | SHRD.CLod(Eaddr, reg) =>
00439         stmts = instantiate(pc,  "SHRD.CLod", DIS_EADDR32, DIS_REG32);
00440 
00441     | SHRD.CLow(Eaddr, reg) =>
00442         stmts = instantiate(pc,  "SHRD.CLow", DIS_EADDR16, DIS_REG16);
00443 
00444     | SHLD.Ibod(Eaddr, reg, count) =>
00445         stmts = instantiate(pc,  "SHLD.Ibod", DIS_EADDR32, DIS_REG32, DIS_COUNT);
00446 
00447     | SHLD.Ibow(Eaddr, reg, count) =>
00448         stmts = instantiate(pc,  "SHLD.Ibow", DIS_EADDR16, DIS_REG16, DIS_COUNT);
00449 
00450     | SHRD.Ibod(Eaddr, reg, count) =>
00451         stmts = instantiate(pc,  "SHRD.Ibod", DIS_EADDR32, DIS_REG32, DIS_COUNT);
00452 
00453     | SHRD.Ibow(Eaddr, reg, count) =>
00454         stmts = instantiate(pc,  "SHRD.Ibow", DIS_EADDR16, DIS_REG16, DIS_COUNT);
00455 
00456     | SIDT(Mem) =>
00457         stmts = instantiate(pc,  "SIDT", DIS_MEM);
00458 
00459     | SGDT(Mem) =>
00460         stmts = instantiate(pc,  "SGDT", DIS_MEM);
00461 
00462     // Sets are now in the high level instructions
00463     | SCASvod() =>
00464         stmts = instantiate(pc,  "SCASvod");
00465 
00466     | SCASvow() =>
00467         stmts = instantiate(pc,  "SCASvow");
00468 
00469     | SCASB() =>
00470         stmts = instantiate(pc,  "SCASB");
00471 
00472     | SAHF() =>
00473         stmts = instantiate(pc,  "SAHF");
00474 
00475     | RSM() =>
00476         stmts = instantiate(pc,  "RSM");
00477 
00478     | RET.far.Iw(i16) =>
00479         stmts = instantiate(pc,  "RET.far.Iw", DIS_I16);
00480         ReturnStatement *ret = new ReturnStatement;
00481         result.rtl = new RTL(pc, stmts);
00482         result.rtl->appendStmt(ret);
00483 
00484     | RET.Iw(i16) =>
00485         stmts = instantiate(pc,  "RET.Iw", DIS_I16);
00486         ReturnStatement *ret = new ReturnStatement;
00487         result.rtl = new RTL(pc, stmts);
00488         result.rtl->appendStmt(ret);
00489 
00490     | RET.far() =>
00491         stmts = instantiate(pc,  "RET.far");
00492         result.rtl = new RTL(pc, stmts);
00493         result.rtl->appendStmt(new ReturnStatement);
00494 
00495     | RET() =>
00496         stmts = instantiate(pc,  "RET");
00497         result.rtl = new RTL(pc, stmts);
00498         result.rtl->appendStmt(new ReturnStatement);
00499 
00500 //   | REPNE() =>
00501 //      stmts = instantiate(pc,  "REPNE");
00502 
00503 //  | REP() =>
00504 //      stmts = instantiate(pc,  "REP");
00505 
00506     | REP.CMPSB()  =>
00507         stmts = instantiate(pc,  name);
00508 
00509     | REP.CMPSvow()  =>
00510         stmts = instantiate(pc,  name);
00511 
00512     | REP.CMPSvod()  =>
00513         stmts = instantiate(pc,  name);
00514 
00515     | REP.LODSB()  =>
00516         stmts = instantiate(pc,  name);
00517 
00518     | REP.LODSvow()  =>
00519         stmts = instantiate(pc,  name);
00520 
00521     | REP.LODSvod()  =>
00522         stmts = instantiate(pc,  name);
00523 
00524     | REP.MOVSB()  =>
00525         stmts = instantiate(pc,  name);
00526 
00527     | REP.MOVSvow()  =>
00528         stmts = instantiate(pc,  name);
00529 
00530     | REP.MOVSvod()  =>
00531         stmts = instantiate(pc,  name);
00532 
00533     | REP.SCASB()  =>
00534         stmts = instantiate(pc,  name);
00535 
00536     | REP.SCASvow()  =>
00537         stmts = instantiate(pc,  name);
00538 
00539     | REP.SCASvod()  =>
00540         stmts = instantiate(pc,  name);
00541 
00542     | REP.STOSB()  =>
00543         stmts = instantiate(pc,  name);
00544 
00545     | REP.STOSvow()  =>
00546         stmts = instantiate(pc,  name);
00547 
00548     | REP.STOSvod()  =>
00549         stmts = instantiate(pc,  name);
00550 
00551     | REPNE.CMPSB()  =>
00552         stmts = instantiate(pc,  name);
00553 
00554     | REPNE.CMPSvow()  =>
00555         stmts = instantiate(pc,  name);
00556 
00557     | REPNE.CMPSvod()  =>
00558         stmts = instantiate(pc,  name);
00559 
00560     | REPNE.LODSB()  =>
00561         stmts = instantiate(pc,  name);
00562 
00563     | REPNE.LODSvow()  =>
00564         stmts = instantiate(pc,  name);
00565 
00566     | REPNE.LODSvod()  =>
00567         stmts = instantiate(pc,  name);
00568 
00569     | REPNE.MOVSB()  =>
00570         stmts = instantiate(pc,  name);
00571 
00572     | REPNE.MOVSvow()  =>
00573         stmts = instantiate(pc,  name);
00574 
00575     | REPNE.MOVSvod()  =>
00576         stmts = instantiate(pc,  name);
00577 
00578     | REPNE.SCASB()  =>
00579         stmts = instantiate(pc,  name);
00580 
00581     | REPNE.SCASvow()  =>
00582         stmts = instantiate(pc,  name);
00583 
00584     | REPNE.SCASvod()  =>
00585         stmts = instantiate(pc,  name);
00586 
00587     | REPNE.STOSB()  =>
00588         stmts = instantiate(pc,  name);
00589 
00590     | REPNE.STOSvow()  =>
00591         stmts = instantiate(pc,  name);
00592 
00593     | REPNE.STOSvod()  =>
00594         stmts = instantiate(pc,  name);
00595 
00596     | RDMSR() =>
00597         stmts = instantiate(pc,  "RDMSR");
00598 
00599     | SARB.Ev.Ibod(Eaddr, i8) =>
00600         stmts = instantiate(pc,  "SARB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00601 
00602     | SARB.Ev.Ibow(Eaddr, i8) =>
00603         stmts = instantiate(pc,  "SARB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00604 
00605     | SHRB.Ev.Ibod(Eaddr, i8) =>
00606         stmts = instantiate(pc,  "SHRB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00607 
00608     | SHRB.Ev.Ibow(Eaddr, i8) =>
00609         stmts = instantiate(pc,  "SHRB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00610 
00611     | SHLSALB.Ev.Ibod(Eaddr, i8) =>
00612         stmts = instantiate(pc,  "SHLSALB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00613 
00614     | SHLSALB.Ev.Ibow(Eaddr, i8) =>
00615         stmts = instantiate(pc,  "SHLSALB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00616 
00617     | RCRB.Ev.Ibod(Eaddr, i8) =>
00618         stmts = instantiate(pc,  "RCRB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00619 
00620     | RCRB.Ev.Ibow(Eaddr, i8) =>
00621         stmts = instantiate(pc,  "RCRB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00622 
00623     | RCLB.Ev.Ibod(Eaddr, i8) =>
00624         stmts = instantiate(pc,  "RCLB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00625 
00626     | RCLB.Ev.Ibow(Eaddr, i8) =>
00627         stmts = instantiate(pc,  "RCLB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00628 
00629     | RORB.Ev.Ibod(Eaddr, i8) =>
00630         stmts = instantiate(pc,  "RORB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00631 
00632     | RORB.Ev.Ibow(Eaddr, i8) =>
00633         stmts = instantiate(pc,  "RORB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00634 
00635     | ROLB.Ev.Ibod(Eaddr, i8) =>
00636         stmts = instantiate(pc,  "ROLB.Ev.Ibod", DIS_EADDR32, DIS_I8);
00637 
00638     | ROLB.Ev.Ibow(Eaddr, i8) =>
00639         stmts = instantiate(pc,  "ROLB.Ev.Ibow", DIS_EADDR16, DIS_I8);
00640 
00641     | SARB.Eb.Ib(Eaddr, i8) =>
00642         stmts = instantiate(pc,  "SARB.Eb.Ib", DIS_EADDR8, DIS_I8);
00643 
00644     | SHRB.Eb.Ib(Eaddr, i8) =>
00645         stmts = instantiate(pc,  "SHRB.Eb.Ib", DIS_EADDR8, DIS_I8);
00646 
00647     | SHLSALB.Eb.Ib(Eaddr, i8) =>
00648         stmts = instantiate(pc,  "SHLSALB.Eb.Ib", DIS_EADDR8, DIS_I8);
00649 
00650     | RCRB.Eb.Ib(Eaddr, i8) =>
00651         stmts = instantiate(pc,  "RCRB.Eb.Ib", DIS_EADDR8, DIS_I8);
00652 
00653     | RCLB.Eb.Ib(Eaddr, i8) =>
00654         stmts = instantiate(pc,  "RCLB.Eb.Ib", DIS_EADDR8, DIS_I8);
00655 
00656     | RORB.Eb.Ib(Eaddr, i8) =>
00657         stmts = instantiate(pc,  "RORB.Eb.Ib", DIS_EADDR8, DIS_I8);
00658 
00659     | ROLB.Eb.Ib(Eaddr, i8) =>
00660         stmts = instantiate(pc,  "ROLB.Eb.Ib", DIS_EADDR8, DIS_I8);
00661 
00662     | SARB.Ev.CLod(Eaddr) =>
00663         stmts = instantiate(pc,  "SARB.Ev.CLod", DIS_EADDR32);
00664 
00665     | SARB.Ev.CLow(Eaddr) =>
00666         stmts = instantiate(pc,  "SARB.Ev.CLow", DIS_EADDR16);
00667 
00668     | SARB.Ev.1od(Eaddr) =>
00669         stmts = instantiate(pc,  "SARB.Ev.1od", DIS_EADDR32);
00670 
00671     | SARB.Ev.1ow(Eaddr) =>
00672         stmts = instantiate(pc,  "SARB.Ev.1ow", DIS_EADDR16);
00673 
00674     | SHRB.Ev.CLod(Eaddr) =>
00675         stmts = instantiate(pc,  "SHRB.Ev.CLod", DIS_EADDR32);
00676 
00677     | SHRB.Ev.CLow(Eaddr) =>
00678         stmts = instantiate(pc,  "SHRB.Ev.CLow", DIS_EADDR16);
00679 
00680     | SHRB.Ev.1od(Eaddr) =>
00681         stmts = instantiate(pc,  "SHRB.Ev.1od", DIS_EADDR32);
00682 
00683     | SHRB.Ev.1ow(Eaddr) =>
00684         stmts = instantiate(pc,  "SHRB.Ev.1ow", DIS_EADDR16);
00685 
00686     | SHLSALB.Ev.CLod(Eaddr) =>
00687         stmts = instantiate(pc,  "SHLSALB.Ev.CLod", DIS_EADDR32);
00688 
00689     | SHLSALB.Ev.CLow(Eaddr) =>
00690         stmts = instantiate(pc,  "SHLSALB.Ev.CLow", DIS_EADDR16);
00691 
00692     | SHLSALB.Ev.1od(Eaddr) =>
00693         stmts = instantiate(pc,  "SHLSALB.Ev.1od", DIS_EADDR32);
00694 
00695     | SHLSALB.Ev.1ow(Eaddr) =>
00696         stmts = instantiate(pc,  "SHLSALB.Ev.1ow", DIS_EADDR16);
00697 
00698     | RCRB.Ev.CLod(Eaddr) =>
00699         stmts = instantiate(pc,  "RCRB.Ev.CLod", DIS_EADDR32);
00700 
00701     | RCRB.Ev.CLow(Eaddr) =>
00702         stmts = instantiate(pc,  "RCRB.Ev.CLow", DIS_EADDR16);
00703 
00704     | RCRB.Ev.1od(Eaddr) =>
00705         stmts = instantiate(pc,  "RCRB.Ev.1od", DIS_EADDR32);
00706 
00707     | RCRB.Ev.1ow(Eaddr) =>
00708         stmts = instantiate(pc,  "RCRB.Ev.1ow", DIS_EADDR16);
00709 
00710     | RCLB.Ev.CLod(Eaddr) =>
00711         stmts = instantiate(pc,  "RCLB.Ev.CLod", DIS_EADDR32);
00712 
00713     | RCLB.Ev.CLow(Eaddr) =>
00714         stmts = instantiate(pc,  "RCLB.Ev.CLow", DIS_EADDR16);
00715 
00716     | RCLB.Ev.1od(Eaddr) =>
00717         stmts = instantiate(pc,  "RCLB.Ev.1od", DIS_EADDR32);
00718 
00719     | RCLB.Ev.1ow(Eaddr) =>
00720         stmts = instantiate(pc,  "RCLB.Ev.1ow", DIS_EADDR16);
00721 
00722     | RORB.Ev.CLod(Eaddr) =>
00723         stmts = instantiate(pc,  "RORB.Ev.CLod", DIS_EADDR32);
00724 
00725     | RORB.Ev.CLow(Eaddr) =>
00726         stmts = instantiate(pc,  "RORB.Ev.CLow", DIS_EADDR16);
00727 
00728     | RORB.Ev.1od(Eaddr) =>
00729         stmts = instantiate(pc,  "RORB.Ev.1od", DIS_EADDR32);
00730 
00731     | RORB.Ev.1ow(Eaddr) =>
00732         stmts = instantiate(pc,  "ORB.Ev.1owR", DIS_EADDR16);
00733 
00734     | ROLB.Ev.CLod(Eaddr) =>
00735         stmts = instantiate(pc,  "ROLB.Ev.CLod", DIS_EADDR32);
00736 
00737     | ROLB.Ev.CLow(Eaddr) =>
00738         stmts = instantiate(pc,  "ROLB.Ev.CLow", DIS_EADDR16);
00739 
00740     | ROLB.Ev.1od(Eaddr) =>
00741         stmts = instantiate(pc,  "ROLB.Ev.1od", DIS_EADDR32);
00742 
00743     | ROLB.Ev.1ow(Eaddr) =>
00744         stmts = instantiate(pc,  "ROLB.Ev.1ow", DIS_EADDR16);
00745 
00746     | SARB.Eb.CL(Eaddr) =>
00747         stmts = instantiate(pc,  "SARB.Eb.CL", DIS_EADDR32);
00748 
00749     | SARB.Eb.1(Eaddr) =>
00750         stmts = instantiate(pc,  "SARB.Eb.1", DIS_EADDR16);
00751 
00752     | SHRB.Eb.CL(Eaddr) =>
00753         stmts = instantiate(pc,  "SHRB.Eb.CL", DIS_EADDR8);
00754 
00755     | SHRB.Eb.1(Eaddr) =>
00756         stmts = instantiate(pc,  "SHRB.Eb.1", DIS_EADDR8);
00757 
00758     | SHLSALB.Eb.CL(Eaddr) =>
00759         stmts = instantiate(pc,  "SHLSALB.Eb.CL", DIS_EADDR8);
00760 
00761     | SHLSALB.Eb.1(Eaddr) =>
00762         stmts = instantiate(pc,  "SHLSALB.Eb.1", DIS_EADDR8);
00763 
00764     | RCRB.Eb.CL(Eaddr) =>
00765         stmts = instantiate(pc,  "RCRB.Eb.CL", DIS_EADDR8);
00766 
00767     | RCRB.Eb.1(Eaddr) =>
00768         stmts = instantiate(pc,  "RCRB.Eb.1", DIS_EADDR8);
00769 
00770     | RCLB.Eb.CL(Eaddr) =>
00771         stmts = instantiate(pc,  "RCLB.Eb.CL", DIS_EADDR8);
00772 
00773     | RCLB.Eb.1(Eaddr) =>
00774         stmts = instantiate(pc,  "RCLB.Eb.1", DIS_EADDR8);
00775 
00776     | RORB.Eb.CL(Eaddr) =>
00777         stmts = instantiate(pc,  "RORB.Eb.CL", DIS_EADDR8);
00778 
00779     | RORB.Eb.1(Eaddr) =>
00780         stmts = instantiate(pc,  "RORB.Eb.1", DIS_EADDR8);
00781 
00782     | ROLB.Eb.CL(Eaddr) =>
00783         stmts = instantiate(pc,  "ROLB.Eb.CL", DIS_EADDR8);
00784 
00785     | ROLB.Eb.1(Eaddr) =>
00786         stmts = instantiate(pc,  "ROLB.Eb.1", DIS_EADDR8);
00787 
00788     // There is no SSL for these, so don't call instantiate, it will only
00789     // cause an assert failure. Also, may as well treat these as invalid instr
00790 //    | PUSHFod() =>
00791 //        stmts = instantiate(pc,  "PUSHFod");
00792 
00793 //    | PUSHFow() =>
00794 //        stmts = instantiate(pc,  "PUSHFow");
00795 
00796 //    | PUSHAod() =>
00797 //        stmts = instantiate(pc,  "PUSHAod");
00798 
00799 //    | PUSHAow() =>
00800 //        stmts = instantiate(pc,  "PUSHAow");
00801 
00802     | PUSH.GS() =>
00803         stmts = instantiate(pc,  "PUSH.GS");
00804 
00805     | PUSH.FS() =>
00806         stmts = instantiate(pc,  "PUSH.FS");
00807 
00808     | PUSH.ES() =>
00809         stmts = instantiate(pc,  "PUSH.ES");
00810 
00811     | PUSH.DS() =>
00812         stmts = instantiate(pc,  "PUSH.DS");
00813 
00814     | PUSH.SS() =>
00815         stmts = instantiate(pc,  "PUSH.SS");
00816 
00817     | PUSH.CS() =>
00818         stmts = instantiate(pc,  "PUSH.CS");
00819 
00820     | PUSH.Ivod(i32) =>
00821         stmts = instantiate(pc,  "PUSH.Ivod", DIS_I32);
00822 
00823     | PUSH.Ivow(i16) =>
00824         stmts = instantiate(pc,  "PUSH.Ivow", DIS_I16);
00825 
00826     | PUSH.Ixob(i8) =>
00827         stmts = instantiate(pc,  "PUSH.Ixob", DIS_I8);
00828 
00829     | PUSH.Ixow(i8) =>
00830         stmts = instantiate(pc,  "PUSH.Ixow", DIS_I8);
00831 
00832     | PUSHod(r32) =>
00833         stmts = instantiate(pc,  "PUSHod", DIS_R32);
00834 
00835     | PUSHow(r32) =>
00836         stmts = instantiate(pc,  "PUSHow", DIS_R32);  // Check!
00837 
00838     | PUSH.Evod(Eaddr) =>
00839         stmts = instantiate(pc,  "PUSH.Evod", DIS_EADDR32);
00840 
00841     | PUSH.Evow(Eaddr) =>
00842         stmts = instantiate(pc,  "PUSH.Evow", DIS_EADDR16);
00843 
00844 //    | POPFod() =>
00845 //        stmts = instantiate(pc,  "POPFod");
00846 
00847 //    | POPFow() =>
00848 //        stmts = instantiate(pc,  "POPFow");
00849 
00850 //    | POPAod() =>
00851 //        stmts = instantiate(pc,  "POPAod");
00852 
00853 //    | POPAow() =>
00854 //        stmts = instantiate(pc,  "POPAow");
00855 
00856     | POP.GS() =>
00857         stmts = instantiate(pc,  "POP.GS");
00858 
00859     | POP.FS() =>
00860         stmts = instantiate(pc,  "POP.FS");
00861 
00862     | POP.DS() =>
00863         stmts = instantiate(pc,  "POP.DS");
00864 
00865     | POP.SS() =>
00866         stmts = instantiate(pc,  "POP.SS");
00867 
00868     | POP.ES() =>
00869         stmts = instantiate(pc,  "POP.ES");
00870 
00871     | POPod(r32) =>
00872         stmts = instantiate(pc,  "POPod", DIS_R32);
00873 
00874     | POPow(r32) =>
00875         stmts = instantiate(pc,  "POPow", DIS_R32);   // Check!
00876 
00877     | POP.Evod(Eaddr) =>
00878         stmts = instantiate(pc,  "POP.Evod", DIS_EADDR32);
00879 
00880     | POP.Evow(Eaddr) =>
00881         stmts = instantiate(pc,  "POP.Evow", DIS_EADDR16);
00882 
00883 //    | OUTSvod() =>
00884 //        stmts = instantiate(pc,  "OUTSvod");
00885 
00886 //    | OUTSvow() =>
00887 //        stmts = instantiate(pc,  "OUTSvow");
00888 
00889 //    | OUTSB() =>
00890 //        stmts = instantiate(pc,  "OUTSB");
00891 
00892 //    | OUT.DX.eAXod() =>
00893 //        stmts = instantiate(pc,  "OUT.DX.eAXod");
00894 
00895 //    | OUT.DX.eAXow() =>
00896 //        stmts = instantiate(pc,  "OUT.DX.eAXow");
00897 
00898 //    | OUT.DX.AL() =>
00899 //        stmts = instantiate(pc,  "OUT.DX.AL");
00900 
00901 //    | OUT.Ib.eAXod(i8) =>
00902 //        stmts = instantiate(pc,  "OUT.Ib.eAXod", DIS_I8);
00903 
00904 //    | OUT.Ib.eAXow(i8) =>
00905 //        stmts = instantiate(pc,  "OUT.Ib.eAXow", DIS_I8);
00906 
00907 //    | OUT.Ib.AL(i8) =>
00908 //        stmts = instantiate(pc,  "OUT.Ib.AL", DIS_I8);
00909 
00910     | NOTod(Eaddr) =>
00911         stmts = instantiate(pc,  "NOTod", DIS_EADDR32);
00912 
00913     | NOTow(Eaddr) =>
00914         stmts = instantiate(pc,  "NOTow", DIS_EADDR16);
00915 
00916     | NOTb(Eaddr) =>
00917         stmts = instantiate(pc,  "NOTb", DIS_EADDR8);
00918 
00919     | NEGod(Eaddr) =>
00920         stmts = instantiate(pc,  "NEGod", DIS_EADDR32);
00921 
00922     | NEGow(Eaddr) =>
00923         stmts = instantiate(pc,  "NEGow", DIS_EADDR16);
00924 
00925     | NEGb(Eaddr) =>
00926         stmts = instantiate(pc,  "NEGb", DIS_EADDR8);
00927 
00928     | MUL.AXod(Eaddr) =>
00929         stmts = instantiate(pc,  "MUL.AXod", DIS_EADDR32);
00930 
00931     | MUL.AXow(Eaddr) =>
00932         stmts = instantiate(pc,  "MUL.AXow", DIS_EADDR16);
00933 
00934     | MUL.AL(Eaddr) =>
00935         stmts = instantiate(pc,  "MUL.AL", DIS_EADDR8);
00936 
00937     | MOVZX.Gv.Ew(r32, Eaddr) =>
00938         stmts = instantiate(pc,  "MOVZX.Gv.Ew", DIS_R32, DIS_EADDR16);
00939 
00940     | MOVZX.Gv.Ebod(r32, Eaddr) =>
00941         stmts = instantiate(pc,  "MOVZX.Gv.Ebod", DIS_R32, DIS_EADDR8);
00942 
00943     | MOVZX.Gv.Ebow(r16, Eaddr) =>
00944         stmts = instantiate(pc,  "MOVZX.Gv.Ebow", DIS_R16, DIS_EADDR8);
00945 
00946     | MOVSX.Gv.Ew(r32, Eaddr) =>
00947         stmts = instantiate(pc,  "MOVSX.Gv.Ew", DIS_R32, DIS_EADDR16);
00948 
00949     | MOVSX.Gv.Ebod(r32, Eaddr) =>
00950         stmts = instantiate(pc,  "MOVSX.Gv.Ebod", DIS_R32, DIS_EADDR8);
00951 
00952     | MOVSX.Gv.Ebow(r16, Eaddr) =>
00953         stmts = instantiate(pc,  "MOVZX.Gv.Ebow", DIS_R16, DIS_EADDR8);
00954 
00955     | MOVSvod() =>
00956         stmts = instantiate(pc,  "MOVSvod");
00957 
00958     | MOVSvow() =>
00959         stmts = instantiate(pc,  "MOVSvow");
00960 
00961     | MOVSB() =>
00962         stmts = instantiate(pc,  "MOVSB");
00963 
00964 //    | MOV.Rd.Dd(reg, dr) => 
00965 //        unused(reg); unused(dr);
00966 //        stmts = instantiate(pc,  "UNIMP");
00967 
00968 //    | MOV.Dd.Rd(dr, reg) =>
00969 //        unused(reg); unused(dr);
00970 //        stmts = instantiate(pc,  "UNIMP");
00971 
00972 //    | MOV.Rd.Cd(reg, cr) =>
00973 //        unused(reg); unused(cr);
00974 //        stmts = instantiate(pc,  "UNIMP");
00975 
00976 //    | MOV.Cd.Rd(cr, reg) =>
00977 //        unused(reg); unused(cr);
00978 //        stmts = instantiate(pc,  "UNIMP");
00979 
00980     | MOV.Ed.Ivod(Eaddr, i32) =>
00981         stmts = instantiate(pc,  "MOV.Ed.Ivod", DIS_EADDR32, DIS_I32);
00982 
00983     | MOV.Ew.Ivow(Eaddr, i16) =>
00984         stmts = instantiate(pc,  "MOV.Ew.Ivow", DIS_EADDR16, DIS_I16);
00985 
00986     | MOV.Eb.Ib(Eaddr, i8) =>
00987         stmts = instantiate(pc,  "MOV.Eb.Ib", DIS_EADDR8, DIS_I8);
00988 
00989     | MOVid(r32, i32) =>
00990         stmts = instantiate(pc,  "MOVid", DIS_R32, DIS_I32);
00991 
00992     | MOViw(r16, i16) =>
00993         stmts = instantiate(pc,  "MOViw", DIS_R16, DIS_I16);  // Check!
00994 
00995     | MOVib(r8, i8) =>
00996         stmts = instantiate(pc,  "MOVib", DIS_R8, DIS_I8);
00997 
00998     | MOV.Ov.eAXod(off) =>
00999         stmts = instantiate(pc,  "MOV.Ov.eAXod", DIS_OFF);
01000 
01001     | MOV.Ov.eAXow(off) =>
01002         stmts = instantiate(pc,  "MOV.Ov.eAXow", DIS_OFF);
01003 
01004     | MOV.Ob.AL(off) =>
01005         stmts = instantiate(pc,  "MOV.Ob.AL", DIS_OFF);
01006 
01007     | MOV.eAX.Ovod(off) =>
01008         stmts = instantiate(pc,  "MOV.eAX.Ovod", DIS_OFF);
01009 
01010     | MOV.eAX.Ovow(off) =>
01011         stmts = instantiate(pc,  "MOV.eAX.Ovow", DIS_OFF);
01012 
01013     | MOV.AL.Ob(off) =>
01014         stmts = instantiate(pc,  "MOV.AL.Ob", DIS_OFF);
01015 
01016 //    | MOV.Sw.Ew(Mem, sr16) =>
01017 //        stmts = instantiate(pc,  "MOV.Sw.Ew", DIS_MEM, DIS_SR16);
01018 
01019 //    | MOV.Ew.Sw(Mem, sr16) =>
01020 //        stmts = instantiate(pc,  "MOV.Ew.Sw", DIS_MEM, DIS_SR16);
01021 
01022     | MOVrmod(reg, Eaddr) =>
01023         stmts = instantiate(pc,  "MOVrmod", DIS_REG32, DIS_EADDR32);
01024 
01025     | MOVrmow(reg, Eaddr) =>
01026         stmts = instantiate(pc,  "MOVrmow", DIS_REG16, DIS_EADDR16);
01027 
01028     | MOVrmb(reg, Eaddr) =>
01029         stmts = instantiate(pc,  "MOVrmb", DIS_REG8, DIS_EADDR8);
01030 
01031     | MOVmrod(Eaddr, reg) =>
01032         stmts = instantiate(pc,  "MOVmrod", DIS_EADDR32, DIS_REG32);
01033 
01034     | MOVmrow(Eaddr, reg) =>
01035         stmts = instantiate(pc,  "MOVmrow", DIS_EADDR16, DIS_REG16);
01036 
01037     | MOVmrb(Eaddr, reg) =>
01038         stmts = instantiate(pc,  "MOVmrb", DIS_EADDR8, DIS_REG8);
01039 
01040     | LTR(Eaddr) =>
01041         stmts = instantiate(pc,  "LTR", DIS_EADDR32);
01042 
01043     | LSS(reg, Mem) =>
01044         stmts = instantiate(pc,  "LSS", DIS_REG32, DIS_MEM);
01045 
01046     | LSLod(reg, Eaddr) =>
01047         stmts = instantiate(pc,  "LSLod", DIS_REG32, DIS_EADDR32);
01048 
01049     | LSLow(reg, Eaddr) =>
01050         stmts = instantiate(pc,  "LSLow", DIS_REG16, DIS_EADDR16);
01051 
01052     | LOOPNE(relocd) =>
01053         stmts = instantiate(pc,  "LOOPNE", dis_Num(relocd - hostPC - 2));
01054 
01055     | LOOPE(relocd) =>
01056         stmts = instantiate(pc,  "LOOPE", dis_Num(relocd-hostPC-2));
01057 
01058     | LOOP(relocd) =>
01059         stmts = instantiate(pc,  "LOOP", dis_Num(relocd-hostPC-2));
01060 
01061     | LGS(reg, Mem) =>
01062         stmts = instantiate(pc,  "LGS", DIS_REG32, DIS_MEM);
01063 
01064     | LFS(reg, Mem) =>
01065         stmts = instantiate(pc,  "LFS", DIS_REG32, DIS_MEM);
01066 
01067     | LES(reg, Mem) =>
01068         stmts = instantiate(pc,  "LES", DIS_REG32, DIS_MEM);
01069 
01070     | LEAVE() =>
01071         stmts = instantiate(pc,  "LEAVE");
01072 
01073     | LEAod(reg, Mem) =>
01074         stmts = instantiate(pc,  "LEA.od", DIS_REG32, DIS_MEM);
01075 
01076     | LEAow(reg, Mem) =>
01077         stmts = instantiate(pc,  "LEA.ow", DIS_REG16, DIS_MEM);
01078 
01079     | LDS(reg, Mem) =>
01080         stmts = instantiate(pc,  "LDS", DIS_REG32, DIS_MEM);
01081 
01082     | LARod(reg, Eaddr) =>
01083         stmts = instantiate(pc,  "LAR.od", DIS_REG32, DIS_EADDR32);
01084 
01085     | LARow(reg, Eaddr) =>
01086         stmts = instantiate(pc,  "LAR.ow", DIS_REG16, DIS_EADDR16);
01087 
01088     | LAHF() =>
01089         stmts = instantiate(pc,  "LAHF");
01090 
01091     /* Branches have been handled in decodeInstruction() now */
01092     | IRET() =>
01093         stmts = instantiate(pc,  "IRET");
01094 
01095     | INVLPG(Mem) =>
01096         stmts = instantiate(pc,  "INVLPG", DIS_MEM);
01097 
01098     | INVD() =>
01099         stmts = instantiate(pc,  "INVD");
01100 
01101     | INTO() =>
01102         stmts = instantiate(pc,  "INTO");
01103 
01104     | INT.Ib(i8) =>
01105         stmts = instantiate(pc,  "INT.Ib", DIS_I8);
01106 
01107 // Removing because an invalid instruction is better than trying to
01108 // instantiate this. -trent
01109 //    | INT3() =>
01110 //        stmts = instantiate(pc,  "INT3");
01111 
01112 //    | INSvod() =>
01113 //        stmts = instantiate(pc,  "INSvod");
01114 
01115 //    | INSvow() =>
01116 //        stmts = instantiate(pc,  "INSvow");
01117 
01118 //    | INSB() =>
01119 //        stmts = instantiate(pc,  "INSB");
01120 
01121     | INCod(r32) =>
01122         stmts = instantiate(pc,  "INCod", DIS_R32);
01123 
01124     | INCow(r32) =>
01125         stmts = instantiate(pc,  "INCow", DIS_R32);
01126 
01127     | INC.Evod(Eaddr) =>
01128         stmts = instantiate(pc,  "INC.Evod", DIS_EADDR32);
01129 
01130     | INC.Evow(Eaddr) =>
01131         stmts = instantiate(pc,  "INC.Evow", DIS_EADDR16);
01132 
01133     | INC.Eb(Eaddr) =>
01134         stmts = instantiate(pc,  "INC.Eb", DIS_EADDR8);
01135 
01136 //    | IN.eAX.DXod() =>
01137 //        stmts = instantiate(pc,  "IN.eAX.DXod");
01138 
01139 //    | IN.eAX.DXow() =>
01140 //        stmts = instantiate(pc,  "IN.eAX.DXow");
01141 
01142 //    | IN.AL.DX() =>
01143 //        stmts = instantiate(pc,  "IN.AL.DX");
01144 
01145 //    | IN.eAX.Ibod(i8) =>
01146 //        stmts = instantiate(pc,  "IN.eAX.Ibod", DIS_I8);
01147 
01148 //    | IN.eAX.Ibow(i8) =>
01149 //        stmts = instantiate(pc,  "IN.eAX.Ibow", DIS_I8);
01150 
01151 //    | IN.AL.Ib(i8) =>
01152 //        stmts = instantiate(pc,  "IN.AL.Ib", DIS_I8);
01153 
01154     | IMUL.Ivd(reg, Eaddr, i32) =>
01155         stmts = instantiate(pc,  "IMUL.Ivd", DIS_REG32, DIS_EADDR32, DIS_I32);
01156 
01157     | IMUL.Ivw(reg, Eaddr, i16) =>
01158         stmts = instantiate(pc,  "IMUL.Ivw", DIS_REG16, DIS_EADDR16, DIS_I16);
01159 
01160     | IMUL.Ibod(reg, Eaddr, i8) =>
01161         stmts = instantiate(pc,  "IMUL.Ibod", DIS_REG32, DIS_EADDR32, DIS_I8);
01162 
01163     | IMUL.Ibow(reg, Eaddr, i8) =>
01164         stmts = instantiate(pc,  "IMUL.Ibow", DIS_REG16, DIS_EADDR16, DIS_I8);
01165 
01166     | IMULrmod(reg, Eaddr) =>
01167         stmts = instantiate(pc,  "IMULrmod", DIS_REG32, DIS_EADDR32);
01168 
01169     | IMULrmow(reg, Eaddr) =>
01170         stmts = instantiate(pc,  "IMULrmow", DIS_REG16, DIS_EADDR16);
01171 
01172     | IMULod(Eaddr) =>
01173         stmts = instantiate(pc,  "IMULod", DIS_EADDR32);
01174 
01175     | IMULow(Eaddr) =>
01176         stmts = instantiate(pc,  "IMULow", DIS_EADDR16);
01177 
01178     | IMULb(Eaddr) =>
01179         stmts = instantiate(pc,  "IMULb", DIS_EADDR8);
01180 
01181     | IDIVeAX(Eaddr) =>
01182         stmts = instantiate(pc,  "IDIVeAX", DIS_EADDR32);
01183 
01184     | IDIVAX(Eaddr) =>
01185         stmts = instantiate(pc,  "IDIVAX", DIS_EADDR16);
01186 
01187     | IDIV(Eaddr) =>
01188         stmts = instantiate(pc,  "IDIV", DIS_EADDR8); /* ?? */
01189 
01190 //  | HLT() =>
01191 //      stmts = instantiate(pc,  "HLT");
01192 
01193     | ENTER(i16, i8) =>
01194         stmts = instantiate(pc,  "ENTER", DIS_I16, DIS_I8);
01195 
01196     | DIVeAX(Eaddr) =>
01197         stmts = instantiate(pc,  "DIVeAX", DIS_EADDR32);
01198 
01199     | DIVAX(Eaddr) =>
01200         stmts = instantiate(pc,  "DIVAX", DIS_EADDR16);
01201 
01202     | DIVAL(Eaddr) =>
01203         stmts = instantiate(pc,  "DIVAL", DIS_EADDR8);
01204 
01205     | DECod(r32) =>
01206         stmts = instantiate(pc,  "DECod", DIS_R32);
01207 
01208     | DECow(r32) =>
01209         stmts = instantiate(pc,  "DECow", DIS_R32);
01210 
01211     | DEC.Evod(Eaddr) =>
01212         stmts = instantiate(pc,  "DEC.Evod", DIS_EADDR32);
01213 
01214     | DEC.Evow(Eaddr) =>
01215         stmts = instantiate(pc,  "DEC.Evow", DIS_EADDR16);
01216 
01217     | DEC.Eb(Eaddr) =>
01218         stmts = instantiate(pc,  "DEC.Eb", DIS_EADDR8);
01219 
01220     | DAS() =>
01221         stmts = instantiate(pc,  "DAS");
01222 
01223     | DAA() =>
01224         stmts = instantiate(pc,  "DAA");
01225 
01226     | CDQ() =>
01227         stmts = instantiate(pc,  "CDQ");
01228 
01229     | CWD() =>
01230         stmts = instantiate(pc,  "CWD");
01231 
01232     | CPUID() =>
01233         stmts = instantiate(pc,  "CPUID");
01234 
01235     | CMPXCHG8B(Mem) =>
01236         stmts = instantiate(pc,  "CMPXCHG8B", DIS_MEM);
01237 
01238     | CMPXCHG.Ev.Gvod(Eaddr, reg) =>
01239         stmts = instantiate(pc,  "CMPXCHG.Ev.Gvod", DIS_EADDR32, DIS_REG32);
01240 
01241     | CMPXCHG.Ev.Gvow(Eaddr, reg) =>
01242         stmts = instantiate(pc,  "CMPXCHG.Ev.Gvow", DIS_EADDR16, DIS_REG16);
01243 
01244     | CMPXCHG.Eb.Gb(Eaddr, reg) =>
01245         stmts = instantiate(pc,  "CMPXCHG.Eb.Gb", DIS_EADDR8, DIS_REG8);
01246 
01247     | CMPSvod() =>
01248         stmts = instantiate(pc,  "CMPSvod");
01249 
01250     | CMPSvow() =>
01251         stmts = instantiate(pc,  "CMPSvow");
01252 
01253     | CMPSB() =>
01254         stmts = instantiate(pc,  "CMPSB");
01255 
01256     | CMC() =>
01257         stmts = instantiate(pc,  "CMC");
01258 
01259     | CLTS() =>
01260         stmts = instantiate(pc,  "CLTS");
01261 
01262     | CLI() =>
01263         stmts = instantiate(pc,  "CLI");
01264 
01265     | CLD() =>
01266         stmts = instantiate(pc,  "CLD");
01267 
01268     | CLC() =>
01269         stmts = instantiate(pc,  "CLC");
01270 
01271     | CWDE() =>
01272         stmts = instantiate(pc,  "CWDE");
01273 
01274     | CBW() =>
01275         stmts = instantiate(pc,  "CBW");
01276 
01277     /* Decode the following as a NOP. We see these in startup code, and anywhere
01278         that calls the OS (as lcall 7, 0) */
01279     | CALL.aPod(seg, off) =>
01280         unused(seg); unused(off);
01281         stmts = instantiate(pc, "NOP");
01282 
01283     | CALL.Jvod(relocd) =>
01284         stmts = instantiate(pc,  "CALL.Jvod", dis_Num(relocd));
01285         // Fix the last assignment, which is now %pc := %pc + (K + hostPC)
01286         Assign* last = (Assign*)stmts->back();
01287         Const* reloc = (Const*)((Binary*)last->getRight())->getSubExp2();
01288         assert(reloc->isIntConst());
01289         // Subtract off the host pc
01290         reloc->setInt(reloc->getInt() - hostPC);
01291         ADDRESS nativeDest = relocd-delta;
01292         
01293         if (nativeDest == pc+5) {
01294             // This is a call $+5
01295             // Use the standard semantics, except for the last statement
01296             // (just updates %pc)
01297             stmts->pop_back();
01298             // And don't make it a call statement
01299         } else {
01300             CallStatement* call = new CallStatement;
01301             // Set the destination
01302             call->setDest(nativeDest);
01303             stmts->push_back(call);
01304             Proc* destProc = prog->setNewProc(nativeDest);
01305             if (destProc == (Proc*)-1) destProc = NULL;     // In case a deleted Proc
01306             call->setDestProc(destProc);
01307         }
01308         result.rtl = new RTL(pc, stmts);
01309 
01310     | BTSiod(Eaddr, i8) =>
01311         stmts = instantiate(pc,  "BTSiod", DIS_I8, DIS_EADDR32);
01312 
01313     | BTSiow(Eaddr, i8) =>
01314         stmts = instantiate(pc,  "BTSiow", DIS_I8, DIS_EADDR16);
01315 
01316     | BTSod(Eaddr, reg) =>
01317         stmts = instantiate(pc,  "BTSod", DIS_EADDR32, DIS_REG32);
01318 
01319     | BTSow(Eaddr, reg) =>
01320         stmts = instantiate(pc,  "BTSow", DIS_EADDR16, DIS_REG16);
01321 
01322     | BTRiod(Eaddr, i8) =>
01323         stmts = instantiate(pc,  "BTRiod", DIS_EADDR32, DIS_I8);
01324 
01325     | BTRiow(Eaddr, i8) =>
01326         stmts = instantiate(pc,  "BTRiow", DIS_EADDR16, DIS_I8);
01327 
01328     | BTRod(Eaddr, reg) =>
01329         stmts = instantiate(pc,  "BTRod", DIS_EADDR32, DIS_REG32);
01330 
01331     | BTRow(Eaddr, reg) =>
01332         stmts = instantiate(pc,  "BTRow", DIS_EADDR16, DIS_REG16);
01333 
01334     | BTCiod(Eaddr, i8) =>
01335         stmts = instantiate(pc,  "BTCiod", DIS_EADDR32, DIS_I8);
01336 
01337     | BTCiow(Eaddr, i8) =>
01338         stmts = instantiate(pc,  "BTCiow", DIS_EADDR16, DIS_I8);
01339 
01340     | BTCod(Eaddr, reg) =>
01341         stmts = instantiate(pc,  "BTCod", DIS_EADDR32, DIS_REG32);
01342 
01343     | BTCow(Eaddr, reg) =>
01344         stmts = instantiate(pc,  "BTCow", DIS_EADDR16, DIS_REG16);
01345 
01346     | BTiod(Eaddr, i8) =>
01347         stmts = instantiate(pc,  "BTiod", DIS_EADDR32, DIS_I8);
01348 
01349     | BTiow(Eaddr, i8) =>
01350         stmts = instantiate(pc,  "BTiow", DIS_EADDR16, DIS_I8);
01351 
01352     | BTod(Eaddr, reg) =>
01353         stmts = instantiate(pc,  "BTod", DIS_EADDR32, DIS_REG32);
01354 
01355     | BTow(Eaddr, reg) =>
01356         stmts = instantiate(pc,  "BTow", DIS_EADDR16, DIS_REG16);
01357 
01358     | BSWAP(r32) =>
01359         stmts = instantiate(pc,  "BSWAP", DIS_R32);
01360 
01361     | BSRod(reg, Eaddr) =>
01362         //stmts = instantiate(pc,  "BSRod", DIS_REG32, DIS_EADDR32);
01363         // Bit Scan Forward: need helper function
01364         genBSFR(pc, DIS_REG32, DIS_EADDR32, 32, 32, opMinus, nextPC-hostPC);
01365         return result;
01366 
01367     | BSRow(reg, Eaddr) =>
01368         //stmts = instantiate(pc,  "BSRow", DIS_REG16, DIS_EADDR16);
01369         genBSFR(pc, DIS_REG16, DIS_EADDR16, 16, 16, opMinus, nextPC-hostPC);
01370         return result;
01371 
01372     | BSFod(reg, Eaddr) =>
01373         //stmts = instantiate(pc,  "BSFod", DIS_REG32, DIS_EADDR32);
01374         genBSFR(pc, DIS_REG32, DIS_EADDR32, -1, 32, opPlus, nextPC-hostPC);
01375         return result;
01376 
01377     | BSFow(reg, Eaddr) =>
01378         //stmts = instantiate(pc,  "BSFow", DIS_REG16, DIS_EADDR16);
01379         genBSFR(pc, DIS_REG16, DIS_EADDR16, -1, 16, opPlus, nextPC-hostPC);
01380         return result;
01381 
01382     // Not "user" instructions:
01383 //  | BOUNDod(reg, Mem) =>
01384 //      stmts = instantiate(pc,  "BOUNDod", DIS_REG32, DIS_MEM);
01385 
01386 //  | BOUNDow(reg, Mem) =>
01387 //      stmts = instantiate(pc,  "BOUNDow", DIS_REG16, DIS_MEM);
01388 
01389 //    | ARPL(Eaddr, reg ) =>
01390 //        unused(Eaddr); unused(reg);
01391 //        stmts = instantiate(pc,  "UNIMP");
01392 
01393 //    | AAS() =>
01394 //        stmts = instantiate(pc,  "AAS");
01395 
01396 //    | AAM() =>
01397 //        stmts = instantiate(pc,  "AAM");
01398 
01399 //    | AAD() =>
01400 //        stmts = instantiate(pc,  "AAD");
01401 
01402 //    | AAA() =>
01403 //        stmts = instantiate(pc,  "AAA");
01404 
01405     | CMPrmod(reg, Eaddr) =>
01406         stmts = instantiate(pc,  "CMPrmod", DIS_REG32, DIS_EADDR32);
01407 
01408     | CMPrmow(reg, Eaddr) =>
01409         stmts = instantiate(pc,  "CMPrmow", DIS_REG16, DIS_EADDR16);
01410 
01411     | XORrmod(reg, Eaddr) =>
01412         stmts = instantiate(pc,  "XORrmod", DIS_REG32, DIS_EADDR32);
01413 
01414     | XORrmow(reg, Eaddr) =>
01415         stmts = instantiate(pc,  "XORrmow", DIS_REG16, DIS_EADDR16);
01416 
01417     | SUBrmod(reg, Eaddr) =>
01418         stmts = instantiate(pc,  "SUBrmod", DIS_REG32, DIS_EADDR32);
01419 
01420     | SUBrmow(reg, Eaddr) =>
01421         stmts = instantiate(pc,  "SUBrmow", DIS_REG16, DIS_EADDR16);
01422 
01423     | ANDrmod(reg, Eaddr) =>
01424         stmts = instantiate(pc,  "ANDrmod", DIS_REG32, DIS_EADDR32);
01425 
01426     | ANDrmow(reg, Eaddr) =>
01427         stmts = instantiate(pc,  "ANDrmow", DIS_REG16, DIS_EADDR16);
01428 
01429     | SBBrmod(reg, Eaddr) =>
01430         stmts = instantiate(pc,  "SBBrmod", DIS_REG32, DIS_EADDR32);
01431 
01432     | SBBrmow(reg, Eaddr) =>
01433         stmts = instantiate(pc,  "SBBrmow", DIS_REG16, DIS_EADDR16);
01434 
01435     | ADCrmod(reg, Eaddr) =>
01436         stmts = instantiate(pc,  "ADCrmod", DIS_REG32, DIS_EADDR32);
01437 
01438     | ADCrmow(reg, Eaddr) =>
01439         stmts = instantiate(pc,  "ADCrmow", DIS_REG16, DIS_EADDR16);
01440 
01441     | ORrmod(reg, Eaddr) =>
01442         stmts = instantiate(pc,  "ORrmod", DIS_REG32, DIS_EADDR32);
01443 
01444     | ORrmow(reg, Eaddr) =>
01445         stmts = instantiate(pc,  "ORrmow", DIS_REG16, DIS_EADDR16);
01446 
01447     | ADDrmod(reg, Eaddr) =>
01448         stmts = instantiate(pc,  "ADDrmod", DIS_REG32, DIS_EADDR32);
01449 
01450     | ADDrmow(reg, Eaddr) =>
01451         stmts = instantiate(pc,  "ADDrmow", DIS_REG16, DIS_EADDR16);
01452 
01453     | CMPrmb(r8, Eaddr) =>
01454         stmts = instantiate(pc,  "CMPrmb", DIS_R8, DIS_EADDR8);
01455 
01456     | XORrmb(r8, Eaddr) =>
01457         stmts = instantiate(pc,  "XORrmb", DIS_R8, DIS_EADDR8);
01458 
01459     | SUBrmb(r8, Eaddr) =>
01460         stmts = instantiate(pc,  "SUBrmb", DIS_R8, DIS_EADDR8);
01461 
01462     | ANDrmb(r8, Eaddr) =>
01463         stmts = instantiate(pc,  "ANDrmb", DIS_R8, DIS_EADDR8);
01464 
01465     | SBBrmb(r8, Eaddr) =>
01466         stmts = instantiate(pc,  "SBBrmb", DIS_R8, DIS_EADDR8);
01467 
01468     | ADCrmb(r8, Eaddr) =>
01469         stmts = instantiate(pc,  "ADCrmb", DIS_R8, DIS_EADDR8);
01470 
01471     | ORrmb(r8, Eaddr) =>
01472         stmts = instantiate(pc,  "ORrmb", DIS_R8, DIS_EADDR8);
01473 
01474     | ADDrmb(r8, Eaddr) =>
01475         stmts = instantiate(pc,  "ADDrmb", DIS_R8, DIS_EADDR8);
01476 
01477     | CMPmrod(Eaddr, reg) =>
01478         stmts = instantiate(pc,  "CMPmrod", DIS_EADDR32, DIS_REG32);
01479 
01480     | CMPmrow(Eaddr, reg) =>
01481         stmts = instantiate(pc,  "CMPmrow", DIS_EADDR16, DIS_REG16);
01482 
01483     | XORmrod(Eaddr, reg) =>
01484         stmts = instantiate(pc,  "XORmrod", DIS_EADDR32, DIS_REG32);
01485 
01486     | XORmrow(Eaddr, reg) =>
01487         stmts = instantiate(pc,  "XORmrow", DIS_EADDR16, DIS_REG16);
01488 
01489     | SUBmrod(Eaddr, reg) =>
01490         stmts = instantiate(pc,  "SUBmrod", DIS_EADDR32, DIS_REG32);
01491 
01492     | SUBmrow(Eaddr, reg) =>
01493         stmts = instantiate(pc,  "SUBmrow", DIS_EADDR16, DIS_REG16);
01494 
01495     | ANDmrod(Eaddr, reg) =>
01496         stmts = instantiate(pc,  "ANDmrod", DIS_EADDR32, DIS_REG32);
01497 
01498     | ANDmrow(Eaddr, reg) =>
01499         stmts = instantiate(pc,  "ANDmrow", DIS_EADDR16, DIS_REG16);
01500 
01501     | SBBmrod(Eaddr, reg) =>
01502         stmts = instantiate(pc,  "SBBmrod", DIS_EADDR32, DIS_REG32);
01503 
01504     | SBBmrow(Eaddr, reg) =>
01505         stmts = instantiate(pc,  "SBBmrow", DIS_EADDR16, DIS_REG16);
01506 
01507     | ADCmrod(Eaddr, reg) =>
01508         stmts = instantiate(pc,  "ADCmrod", DIS_EADDR32, DIS_REG32);
01509 
01510     | ADCmrow(Eaddr, reg) =>
01511         stmts = instantiate(pc,  "ADCmrow", DIS_EADDR16, DIS_REG16);
01512 
01513     | ORmrod(Eaddr, reg) =>
01514         stmts = instantiate(pc,  "ORmrod", DIS_EADDR32, DIS_REG32);
01515 
01516     | ORmrow(Eaddr, reg) =>
01517         stmts = instantiate(pc,  "ORmrow", DIS_EADDR16, DIS_REG16);
01518 
01519     | ADDmrod(Eaddr, reg) =>
01520         stmts = instantiate(pc,  "ADDmrod", DIS_EADDR32, DIS_REG32);
01521 
01522     | ADDmrow(Eaddr, reg) =>
01523         stmts = instantiate(pc,  "ADDmrow", DIS_EADDR16, DIS_REG16);
01524 
01525     | CMPmrb(Eaddr, r8) =>
01526         stmts = instantiate(pc,  "CMPmrb", DIS_EADDR8, DIS_R8);
01527 
01528     | XORmrb(Eaddr, r8) =>
01529         stmts = instantiate(pc,  "XORmrb", DIS_EADDR8, DIS_R8);
01530 
01531     | SUBmrb(Eaddr, r8) =>
01532         stmts = instantiate(pc,  "SUBmrb", DIS_EADDR8, DIS_R8);
01533 
01534     | ANDmrb(Eaddr, r8) =>
01535         stmts = instantiate(pc,  "ANDmrb", DIS_EADDR8, DIS_R8);
01536 
01537     | SBBmrb(Eaddr, r8) =>
01538         stmts = instantiate(pc,  "SBBmrb", DIS_EADDR8, DIS_R8);
01539 
01540     | ADCmrb(Eaddr, r8) =>
01541         stmts = instantiate(pc,  "ADCmrb", DIS_EADDR8, DIS_R8);
01542 
01543     | ORmrb(Eaddr, r8) =>
01544         stmts = instantiate(pc,  "ORmrb", DIS_EADDR8, DIS_R8);
01545 
01546     | ADDmrb(Eaddr, r8) =>
01547         stmts = instantiate(pc,  "ADDmrb", DIS_EADDR8, DIS_R8);
01548 
01549     | CMPiodb(Eaddr, i8) =>
01550         stmts = instantiate(pc,  "CMPiodb", DIS_EADDR32, DIS_I8);
01551 
01552     | CMPiowb(Eaddr, i8) =>
01553         stmts = instantiate(pc,  "CMPiowb", DIS_EADDR16, DIS_I8);
01554 
01555     | XORiodb(Eaddr, i8) =>
01556         stmts = instantiate(pc,  "XORiodb", DIS_EADDR32, DIS_I8);
01557 
01558     | XORiowb(Eaddr, i8) =>
01559         stmts = instantiate(pc,  "XORiowb", DIS_EADDR16, DIS_I8);
01560 
01561     | SUBiodb(Eaddr, i8) =>
01562         stmts = instantiate(pc,  "SUBiodb", DIS_EADDR32, DIS_I8);
01563 
01564     | SUBiowb(Eaddr, i8) =>
01565         stmts = instantiate(pc,  "SUBiowb", DIS_EADDR16, DIS_I8);
01566 
01567     | ANDiodb(Eaddr, i8) =>
01568         // Special hack to ignore and $0xfffffff0, %esp
01569         Exp* oper = dis_Eaddr(Eaddr, 32);
01570         if (i8 != -16 || !(*oper == *Location::regOf(28)))
01571             stmts = instantiate(pc,  "ANDiodb", DIS_EADDR32, DIS_I8);
01572 
01573     | ANDiowb(Eaddr, i8) =>
01574         stmts = instantiate(pc,  "ANDiowb", DIS_EADDR16, DIS_I8);
01575 
01576     | SBBiodb(Eaddr, i8) =>
01577         stmts = instantiate(pc,  "SBBiodb", DIS_EADDR32, DIS_I8);
01578 
01579     | SBBiowb(Eaddr, i8) =>
01580         stmts = instantiate(pc,  "SBBiowb", DIS_EADDR16, DIS_I8);
01581 
01582     | ADCiodb(Eaddr, i8) =>
01583         stmts = instantiate(pc,  "ADCiodb", DIS_EADDR32, DIS_I8);
01584 
01585     | ADCiowb(Eaddr, i8) =>
01586         stmts = instantiate(pc,  "ADCiowb", DIS_EADDR16, DIS_I8);
01587 
01588     | ORiodb(Eaddr, i8) =>
01589         stmts = instantiate(pc,  "ORiodb", DIS_EADDR32, DIS_I8);
01590 
01591     | ORiowb(Eaddr, i8) =>
01592         stmts = instantiate(pc,  "ORiowb", DIS_EADDR16, DIS_I8);
01593 
01594     | ADDiodb(Eaddr, i8) =>
01595         stmts = instantiate(pc,  "ADDiodb", DIS_EADDR32, DIS_I8);
01596 
01597     | ADDiowb(Eaddr, i8) =>
01598         stmts = instantiate(pc,  "ADDiowb", DIS_EADDR16, DIS_I8);
01599 
01600     | CMPid(Eaddr, i32) =>
01601         stmts = instantiate(pc,  "CMPid", DIS_EADDR32, DIS_I32);
01602 
01603     | XORid(Eaddr, i32) =>
01604         stmts = instantiate(pc,  "XORid", DIS_EADDR32, DIS_I32);
01605 
01606     | SUBid(Eaddr, i32) =>
01607         stmts = instantiate(pc,  "SUBid", DIS_EADDR32, DIS_I32);
01608 
01609     | ANDid(Eaddr, i32) =>
01610         stmts = instantiate(pc,  "ANDid", DIS_EADDR32, DIS_I32);
01611 
01612     | SBBid(Eaddr, i32) =>
01613         stmts = instantiate(pc,  "SBBid", DIS_EADDR32, DIS_I32);
01614 
01615     | ADCid(Eaddr, i32) =>
01616         stmts = instantiate(pc,  "ADCid", DIS_EADDR32, DIS_I32);
01617 
01618     | ORid(Eaddr, i32) =>
01619         stmts = instantiate(pc,  "ORid", DIS_EADDR32, DIS_I32);
01620 
01621     | ADDid(Eaddr, i32) =>
01622         stmts = instantiate(pc,  "ADDid", DIS_EADDR32, DIS_I32);
01623 
01624     | CMPiw(Eaddr, i16) =>
01625         stmts = instantiate(pc,  "CMPiw", DIS_EADDR16, DIS_I16);
01626 
01627     | XORiw(Eaddr, i16) =>
01628         stmts = instantiate(pc,  "XORiw", DIS_EADDR16, DIS_I16);
01629 
01630     | SUBiw(Eaddr, i16) =>
01631         stmts = instantiate(pc,  "SUBiw", DIS_EADDR16, DIS_I16);
01632 
01633     | ANDiw(Eaddr, i16) =>
01634         stmts = instantiate(pc,  "ANDiw", DIS_EADDR16, DIS_I16);
01635 
01636     | SBBiw(Eaddr, i16) =>
01637         stmts = instantiate(pc,  "SBBiw", DIS_EADDR16, DIS_I16);
01638 
01639     | ADCiw(Eaddr, i16) =>
01640         stmts = instantiate(pc,  "ADCiw", DIS_EADDR16, DIS_I16);
01641 
01642     | ORiw(Eaddr, i16) =>
01643         stmts = instantiate(pc,  "ORiw", DIS_EADDR16, DIS_I16);
01644 
01645     | ADDiw(Eaddr, i16) =>
01646         stmts = instantiate(pc,  "ADDiw", DIS_EADDR16, DIS_I16);
01647 
01648     | CMPib(Eaddr, i8) =>
01649         stmts = instantiate(pc,  "CMPib", DIS_EADDR8, DIS_I8);
01650 
01651     | XORib(Eaddr, i8) =>
01652         stmts = instantiate(pc,  "XORib", DIS_EADDR8, DIS_I8);
01653 
01654     | SUBib(Eaddr, i8) =>
01655         stmts = instantiate(pc,  "SUBib", DIS_EADDR8, DIS_I8);
01656 
01657     | ANDib(Eaddr, i8) =>
01658         stmts = instantiate(pc,  "ANDib", DIS_EADDR8, DIS_I8);
01659 
01660     | SBBib(Eaddr, i8) =>
01661         stmts = instantiate(pc,  "SBBib", DIS_EADDR8, DIS_I8);
01662 
01663     | ADCib(Eaddr, i8) =>
01664         stmts = instantiate(pc,  "ADCib", DIS_EADDR8, DIS_I8);
01665 
01666     | ORib(Eaddr, i8) =>
01667         stmts = instantiate(pc,  "ORib", DIS_EADDR8, DIS_I8);
01668 
01669     | ADDib(Eaddr, i8) =>
01670         stmts = instantiate(pc,  "ADDib", DIS_EADDR8, DIS_I8);
01671 
01672     | CMPiEAX(i32) =>
01673         stmts = instantiate(pc,  "CMPiEAX", DIS_I32);
01674 
01675     | XORiEAX(i32) =>
01676         stmts = instantiate(pc,  "XORiEAX", DIS_I32);
01677 
01678     | SUBiEAX(i32) =>
01679         stmts = instantiate(pc,  "SUBiEAX", DIS_I32);
01680 
01681     | ANDiEAX(i32) =>
01682         stmts = instantiate(pc,  "ANDiEAX", DIS_I32);
01683 
01684     | SBBiEAX(i32) =>
01685         stmts = instantiate(pc,  "SBBiEAX", DIS_I32);
01686 
01687     | ADCiEAX(i32) =>
01688         stmts = instantiate(pc,  "ADCiEAX", DIS_I32);
01689 
01690     | ORiEAX(i32) =>
01691         stmts = instantiate(pc,  "ORiEAX", DIS_I32);
01692 
01693     | ADDiEAX(i32) =>
01694         stmts = instantiate(pc,  "ADDiEAX", DIS_I32);
01695 
01696     | CMPiAX(i16) =>
01697         stmts = instantiate(pc,  "CMPiAX", DIS_I16);
01698 
01699     | XORiAX(i16) =>
01700         stmts = instantiate(pc,  "XORiAX", DIS_I16);
01701 
01702     | SUBiAX(i16) =>
01703         stmts = instantiate(pc,  "SUBiAX", DIS_I16);
01704 
01705     | ANDiAX(i16) =>
01706         stmts = instantiate(pc,  "ANDiAX", DIS_I16);
01707 
01708     | SBBiAX(i16) =>
01709         stmts = instantiate(pc,  "SBBiAX", DIS_I16);
01710 
01711     | ADCiAX(i16) =>
01712         stmts = instantiate(pc,  "ADCiAX", DIS_I16);
01713 
01714     | ORiAX(i16) =>
01715         stmts = instantiate(pc,  "ORiAX", DIS_I16);
01716 
01717     | ADDiAX(i16) =>
01718         stmts = instantiate(pc,  "ADDiAX", DIS_I16);
01719 
01720     | CMPiAL(i8) =>
01721         stmts = instantiate(pc,  "CMPiAL", DIS_I8);
01722 
01723     | XORiAL(i8) =>
01724         stmts = instantiate(pc,  "XORiAL", DIS_I8);
01725 
01726     | SUBiAL(i8) =>
01727         stmts = instantiate(pc,  "SUBiAL", DIS_I8);
01728 
01729     | ANDiAL(i8) =>
01730         stmts = instantiate(pc,  "ANDiAL", DIS_I8);
01731 
01732     | SBBiAL(i8) =>
01733         stmts = instantiate(pc,  "SBBiAL", DIS_I8);
01734 
01735     | ADCiAL(i8) =>
01736         stmts = instantiate(pc,  "ADCiAL", DIS_I8);
01737 
01738     | ORiAL(i8) =>
01739         stmts = instantiate(pc,  "ORiAL", DIS_I8);
01740 
01741     | ADDiAL(i8) =>
01742         stmts = instantiate(pc,  "ADDiAL", DIS_I8);
01743 
01744     | LODSvod() =>
01745         stmts = instantiate(pc,  "LODSvod");
01746 
01747     | LODSvow() =>
01748         stmts = instantiate(pc,  "LODSvow");
01749 
01750     | LODSB() =>
01751         stmts = instantiate(pc,  "LODSB");
01752 
01753     /* Floating point instructions */
01754     | F2XM1() =>
01755         stmts = instantiate(pc,  "F2XM1");
01756 
01757     | FABS() =>
01758         stmts = instantiate(pc,  "FABS");
01759 
01760     | FADD.R32(Mem32) =>
01761         stmts = instantiate(pc,  "FADD.R32", DIS_MEM32);
01762 
01763     | FADD.R64(Mem64) =>
01764         stmts = instantiate(pc,  "FADD.R64", DIS_MEM64);
01765 
01766     | FADD.ST.STi(idx) =>
01767         stmts = instantiate(pc,  "FADD.St.STi", DIS_IDX);
01768 
01769     | FADD.STi.ST(idx) =>
01770         stmts = instantiate(pc,  "FADD.STi.ST", DIS_IDX);
01771 
01772     | FADDP.STi.ST(idx) =>
01773         stmts = instantiate(pc,  "FADDP.STi.ST", DIS_IDX);
01774 
01775     | FIADD.I32(Mem32) =>
01776         stmts = instantiate(pc,  "FIADD.I32", DIS_MEM32);
01777 
01778     | FIADD.I16(Mem16) =>
01779         stmts = instantiate(pc,  "FIADD.I16", DIS_MEM16);
01780 
01781     | FBLD(Mem80) =>
01782         stmts = instantiate(pc,  "FBLD", DIS_MEM80);
01783 
01784     | FBSTP(Mem80) =>
01785         stmts = instantiate(pc,  "FBSTP", DIS_MEM80);
01786 
01787     | FCHS() =>
01788         stmts = instantiate(pc,  "FCHS");
01789 
01790     | FNCLEX() =>
01791         stmts = instantiate(pc,  "FNCLEX");
01792 
01793     | FCOM.R32(Mem32) =>
01794         stmts = instantiate(pc,  "FCOM.R32", DIS_MEM32);
01795 
01796     | FCOM.R64(Mem64) =>
01797         stmts = instantiate(pc,  "FCOM.R64", DIS_MEM64);
01798 
01799     | FICOM.I32(Mem32) =>
01800         stmts = instantiate(pc,  "FICOM.I32", DIS_MEM32);
01801 
01802     | FICOM.I16(Mem16) =>
01803         stmts = instantiate(pc,  "FICOM.I16", DIS_MEM16);
01804 
01805     | FCOMP.R32(Mem32) =>
01806         stmts = instantiate(pc,  "FCOMP.R32", DIS_MEM32);
01807 
01808     | FCOMP.R64(Mem64) =>
01809         stmts = instantiate(pc,  "FCOMP.R64", DIS_MEM64);
01810 
01811     | FCOM.ST.STi(idx) =>
01812         stmts = instantiate(pc,  "FCOM.ST.STi", DIS_IDX);
01813 
01814     | FCOMP.ST.STi(idx) =>
01815         stmts = instantiate(pc,  "FCOMP.ST.STi", DIS_IDX);
01816 
01817     | FICOMP.I32(Mem32) =>
01818         stmts = instantiate(pc,  "FICOMP.I32", DIS_MEM32);
01819 
01820     | FICOMP.I16(Mem16) =>
01821         stmts = instantiate(pc,  "FICOMP.I16", DIS_MEM16);
01822 
01823     | FCOMPP() =>
01824         stmts = instantiate(pc,  "FCOMPP");
01825 
01826     | FCOMI.ST.STi(idx)  =>
01827         stmts = instantiate(pc, name, DIS_IDX);
01828 
01829     | FCOMIP.ST.STi(idx)  =>
01830         stmts = instantiate(pc, name, DIS_IDX);
01831 
01832     | FCOS() =>
01833         stmts = instantiate(pc,  "FCOS");
01834 
01835     | FDECSTP() =>
01836         stmts = instantiate(pc,  "FDECSTP");
01837 
01838     | FDIV.R32(Mem32) =>
01839         stmts = instantiate(pc,  "FDIV.R32", DIS_MEM32);
01840 
01841     | FDIV.R64(Mem64) =>
01842         stmts = instantiate(pc,  "FDIV.R64", DIS_MEM64);
01843 
01844     | FDIV.ST.STi(idx) =>
01845         stmts = instantiate(pc,  "FDIV.ST.STi", DIS_IDX);
01846 
01847     | FDIV.STi.ST(idx) =>
01848         stmts = instantiate(pc,  "FDIV.STi.ST", DIS_IDX);
01849 
01850     | FDIVP.STi.ST(idx) =>
01851         stmts = instantiate(pc,  "FDIVP.STi.ST", DIS_IDX);
01852 
01853     | FIDIV.I32(Mem32) =>
01854         stmts = instantiate(pc,  "FIDIV.I32", DIS_MEM32);
01855 
01856     | FIDIV.I16(Mem16) =>
01857         stmts = instantiate(pc,  "FIDIV.I16", DIS_MEM16);
01858 
01859     | FDIVR.R32(Mem32) =>
01860         stmts = instantiate(pc,  "FDIVR.R32", DIS_MEM32);
01861 
01862     | FDIVR.R64(Mem64) =>
01863         stmts = instantiate(pc,  "FDIVR.R64", DIS_MEM64);
01864 
01865     | FDIVR.ST.STi(idx) =>
01866         stmts = instantiate(pc,  "FDIVR.ST.STi", DIS_IDX);
01867 
01868     | FDIVR.STi.ST(idx) =>
01869         stmts = instantiate(pc,  "FDIVR.STi.ST", DIS_IDX);
01870 
01871     | FIDIVR.I32(Mem32) =>
01872         stmts = instantiate(pc,  "FIDIVR.I32", DIS_MEM32);
01873 
01874     | FIDIVR.I16(Mem16) =>
01875         stmts = instantiate(pc,  "FIDIVR.I16", DIS_MEM16);
01876 
01877     | FDIVRP.STi.ST(idx) =>
01878         stmts = instantiate(pc,  "FDIVRP.STi.ST", DIS_IDX);
01879 
01880     | FFREE(idx) =>
01881         stmts = instantiate(pc,  "FFREE", DIS_IDX);
01882 
01883     | FILD.lsI16(Mem16) =>
01884         stmts = instantiate(pc,  "FILD.lsI16", DIS_MEM16);
01885 
01886     | FILD.lsI32(Mem32) =>
01887         stmts = instantiate(pc,  "FILD.lsI32", DIS_MEM32);
01888 
01889     | FILD64(Mem64) =>
01890         stmts = instantiate(pc,  "FILD.lsI64", DIS_MEM64);
01891 
01892     | FINIT() =>
01893         stmts = instantiate(pc,  "FINIT");
01894 
01895     | FIST.lsI16(Mem16) =>
01896         stmts = instantiate(pc,  "FIST.lsI16", DIS_MEM16);
01897 
01898     | FIST.lsI32(Mem32) =>
01899         stmts = instantiate(pc,  "FIST.lsI32", DIS_MEM32);
01900 
01901     | FISTP.lsI16(Mem16) =>
01902         stmts = instantiate(pc,  "FISTP.lsI16", DIS_MEM16);
01903 
01904     | FISTP.lsI32(Mem32) =>
01905         stmts = instantiate(pc,  "FISTP.lsI32", DIS_MEM32);
01906 
01907     | FISTP64(Mem64) =>
01908         stmts = instantiate(pc,  "FISTP64", DIS_MEM64);
01909 
01910     | FLD.lsR32(Mem32) =>
01911         stmts = instantiate(pc,  "FLD.lsR32", DIS_MEM32);
01912 
01913     | FLD.lsR64(Mem64) =>
01914         stmts = instantiate(pc,  "FLD.lsR64", DIS_MEM64);
01915 
01916     | FLD80(Mem80) =>
01917         stmts = instantiate(pc,  "FLD80", DIS_MEM80);
01918 
01919 /* This is a bit tricky. The FPUSH logically comes between the read of STi and
01920 # the write to ST0. In particular, FLD ST0 is supposed to duplicate the TOS.
01921 # This problem only happens with this load instruction, so there is a work
01922 # around here that gives us the SSL a value of i that is one more than in
01923 # the instruction */
01924     | FLD.STi(idx) =>
01925         stmts = instantiate(pc,  "FLD.STi", DIS_IDXP1);
01926 
01927     | FLD1() =>
01928         stmts = instantiate(pc,  "FLD1");
01929 
01930     | FLDL2T() =>
01931         stmts = instantiate(pc,  "FLDL2T");
01932 
01933     | FLDL2E() =>
01934         stmts = instantiate(pc,  "FLDL2E");
01935 
01936     | FLDPI() =>
01937         stmts = instantiate(pc,  "FLDPI");
01938 
01939     | FLDLG2() =>
01940         stmts = instantiate(pc,  "FLDLG2");
01941 
01942     | FLDLN2() =>
01943         stmts = instantiate(pc,  "FLDLN2");
01944 
01945     | FLDZ() =>
01946         stmts = instantiate(pc,  "FLDZ");
01947 
01948     | FLDCW(Mem16) =>
01949         stmts = instantiate(pc,  "FLDCW", DIS_MEM16);
01950 
01951     | FLDENV(Mem) =>
01952         stmts = instantiate(pc,  "FLDENV", DIS_MEM);
01953 
01954     | FMUL.R32(Mem32) =>
01955         stmts = instantiate(pc,  "FMUL.R32", DIS_MEM32);
01956 
01957     | FMUL.R64(Mem64) =>
01958         stmts = instantiate(pc,  "FMUL.R64", DIS_MEM64);
01959 
01960     | FMUL.ST.STi(idx) =>
01961         stmts = instantiate(pc,  "FMUL.ST.STi", DIS_IDX);
01962 
01963     | FMUL.STi.ST(idx) =>
01964         stmts = instantiate(pc,  "FMUL.STi.ST", DIS_IDX);
01965 
01966     | FMULP.STi.ST(idx) =>
01967         stmts = instantiate(pc,  "FMULP.STi.ST", DIS_IDX);
01968 
01969     | FIMUL.I32(Mem32) =>
01970         stmts = instantiate(pc,  "FIMUL.I32", DIS_MEM32);
01971 
01972     | FIMUL.I16(Mem16) =>
01973         stmts = instantiate(pc,  "FIMUL.I16", DIS_MEM16);
01974 
01975     | FNOP() =>
01976         stmts = instantiate(pc,  "FNOP");
01977 
01978     | FPATAN() =>
01979         stmts = instantiate(pc,  "FPATAN");
01980 
01981     | FPREM() =>
01982         stmts = instantiate(pc,  "FPREM");
01983 
01984     | FPREM1() =>
01985         stmts = instantiate(pc,  "FPREM1");
01986 
01987     | FPTAN() =>
01988         stmts = instantiate(pc,  "FPTAN");
01989 
01990     | FRNDINT() =>
01991         stmts = instantiate(pc,  "FRNDINT");
01992 
01993     | FRSTOR(Mem) =>
01994         stmts = instantiate(pc,  "FRSTOR", DIS_MEM);
01995 
01996     | FNSAVE(Mem) =>
01997         stmts = instantiate(pc,  "FNSAVE", DIS_MEM);
01998 
01999     | FSCALE() =>
02000         stmts = instantiate(pc,  "FSCALE");
02001 
02002     | FSIN() =>
02003         stmts = instantiate(pc,  "FSIN");
02004 
02005     | FSINCOS() =>
02006         stmts = instantiate(pc,  "FSINCOS");
02007 
02008     | FSQRT() =>
02009         stmts = instantiate(pc,  "FSQRT");
02010 
02011     | FST.lsR32(Mem32) =>
02012         stmts = instantiate(pc,  "FST.lsR32", DIS_MEM32);
02013 
02014     | FST.lsR64(Mem64) =>
02015         stmts = instantiate(pc,  "FST.lsR64", DIS_MEM64);
02016 
02017     | FSTP.lsR32(Mem32) =>
02018         stmts = instantiate(pc,  "FSTP.lsR32", DIS_MEM32);
02019 
02020     | FSTP.lsR64(Mem64) =>
02021         stmts = instantiate(pc,  "FSTP.lsR64", DIS_MEM64);
02022 
02023     | FSTP80(Mem80) =>
02024         stmts = instantiate(pc,  "FSTP80", DIS_MEM80);
02025 
02026     | FST.st.STi(idx) =>
02027         stmts = instantiate(pc,  "FST.st.STi", DIS_IDX);
02028 
02029     | FSTP.st.STi(idx) =>
02030         stmts = instantiate(pc,  "FSTP.st.STi", DIS_IDX);
02031 
02032     | FSTCW(Mem16) =>
02033         stmts = instantiate(pc,  "FSTCW", DIS_MEM16);
02034 
02035     | FSTENV(Mem) =>
02036         stmts = instantiate(pc,  "FSTENV", DIS_MEM);
02037 
02038     | FSTSW(Mem16) =>
02039         stmts = instantiate(pc,  "FSTSW", DIS_MEM16);
02040 
02041     | FSTSW.AX() =>
02042         stmts = instantiate(pc,  "FSTSW.AX");
02043 
02044     | FSUB.R32(Mem32) =>
02045         stmts = instantiate(pc,  "FSUB.R32", DIS_MEM32);
02046 
02047     | FSUB.R64(Mem64) =>
02048         stmts = instantiate(pc,  "FSUB.R64", DIS_MEM64);
02049 
02050     | FSUB.ST.STi(idx) =>
02051         stmts = instantiate(pc,  "FSUB.ST.STi", DIS_IDX);
02052 
02053     | FSUB.STi.ST(idx) =>
02054         stmts = instantiate(pc,  "FSUB.STi.ST", DIS_IDX);
02055 
02056     | FISUB.I32(Mem32) =>
02057         stmts = instantiate(pc,  "FISUB.I32", DIS_MEM32);
02058 
02059     | FISUB.I16(Mem16) =>
02060         stmts = instantiate(pc,  "FISUB.I16", DIS_MEM16);
02061 
02062     | FSUBP.STi.ST(idx) =>
02063         stmts = instantiate(pc,  "FSUBP.STi.ST", DIS_IDX);
02064 
02065     | FSUBR.R32(Mem32) =>
02066         stmts = instantiate(pc,  "FSUBR.R32", DIS_MEM32);
02067 
02068     | FSUBR.R64(Mem64) =>
02069         stmts = instantiate(pc,  "FSUBR.R64", DIS_MEM64);
02070 
02071     | FSUBR.ST.STi(idx) =>
02072         stmts = instantiate(pc,  "FSUBR.ST.STi", DIS_IDX);
02073 
02074     | FSUBR.STi.ST(idx) =>
02075         stmts = instantiate(pc,  "FSUBR.STi.ST", DIS_IDX);
02076 
02077     | FISUBR.I32(Mem32) =>
02078         stmts = instantiate(pc,  "FISUBR.I32", DIS_MEM32);
02079 
02080     | FISUBR.I16(Mem16) =>
02081         stmts = instantiate(pc,  "FISUBR.I16", DIS_MEM16);
02082 
02083     | FSUBRP.STi.ST(idx) =>
02084         stmts = instantiate(pc,  "FSUBRP.STi.ST", DIS_IDX);
02085 
02086     | FTST() =>
02087         stmts = instantiate(pc,  "FTST");
02088 
02089     | FUCOM(idx) =>
02090         stmts = instantiate(pc,  "FUCOM", DIS_IDX);
02091 
02092     | FUCOMP(idx) =>
02093         stmts = instantiate(pc,  "FUCOMP", DIS_IDX);
02094 
02095     | FUCOMPP() =>
02096         stmts = instantiate(pc,  "FUCOMPP");
02097 
02098     | FUCOMI.ST.STi(idx)  =>
02099         stmts = instantiate(pc, name, DIS_IDX);
02100 
02101     | FUCOMIP.ST.STi(idx)  =>
02102         stmts = instantiate(pc, name, DIS_IDX);
02103 
02104     | FXAM() =>
02105         stmts = instantiate(pc,  "FXAM");
02106 
02107     | FXCH(idx) =>
02108         stmts = instantiate(pc,  "FXCH", DIS_IDX);
02109 
02110     | FXTRACT() =>
02111         stmts = instantiate(pc,  "FXTRACT");
02112 
02113     | FYL2X() =>
02114         stmts = instantiate(pc,  "FYL2X");
02115 
02116     | FYL2XP1() =>
02117         stmts = instantiate(pc,  "FYL2XP1");
02118 
02119     else
02120         result.valid = false;       // Invalid instruction
02121         result.rtl = NULL;
02122         result.numBytes = 0;
02123         return result;
02124     endmatch
02125 
02126     if (result.rtl == 0)
02127         result.rtl = new RTL(pc, stmts);
02128     result.numBytes = nextPC - hostPC;
02129     return result;
02130 }
02131 
02132 /*==============================================================================
02133  * These are machine specific functions used to decode instruction operands into Exp*s.
02134  *============================================================================*/
02135 
02136 /*==============================================================================
02137  * FUNCTION:        dis_Mem
02138  * OVERVIEW:        Converts a dynamic address to a Exp* expression.
02139  *                  E.g. [1000] --> m[, 1000
02140  * PARAMETERS:      pc - the address of the Eaddr part of the instr
02141  *                  expr - the expression that will be built
02142  * RETURNS:         the Exp* representation of the given Eaddr
02143  *============================================================================*/
02144 Exp* PentiumDecoder::dis_Mem(ADDRESS pc)
02145 {
02146     Exp* expr = NULL;
02147     lastDwordLc = (unsigned)-1;
02148 
02149     match pc to 
02150     | Abs32 (a) =>
02151             // [a]
02152             expr = Location::memOf(addReloc(new Const(a)));
02153     | Disp32 (d, base) => 
02154             // m[ r[ base] + d]
02155             expr = Location::memOf(new Binary(opPlus,
02156                     dis_Reg(24+base),
02157                     addReloc(new Const(d))));
02158     | Disp8 (d, r32) => 
02159             // m[ r[ r32] + d]
02160             expr = Location::memOf(new Binary(opPlus,
02161                     dis_Reg(24+r32),
02162                     addReloc(new Const(d))));
02163     | Index (base, index, ss) =>
02164             // m[ r[base] + r[index] * ss]
02165             expr = Location::memOf(new Binary(opPlus,
02166                     dis_Reg(24+base),
02167                     new Binary(opMult,
02168                         dis_Reg(24+index),
02169                         new Const(1<<ss))));
02170     | Base (base) =>
02171             // m[ r[base] ]
02172             expr = Location::memOf(dis_Reg(24+base));
02173     | Index32 (d, base, index, ss) =>
02174             // m[ r[ base ] + r[ index ] * ss + d ]
02175             expr = Location::memOf(new Binary(opPlus,
02176                     dis_Reg(24+base),
02177                     new Binary(opPlus,
02178                         new Binary(opMult,
02179                             dis_Reg(24+index),
02180                             new Const(1<<ss)),
02181                         addReloc(new Const(d)))));
02182     | Base32 (d, base) =>
02183             // m[ r[ base] + d ]
02184             expr = Location::memOf(new Binary(opPlus,
02185                     dis_Reg(24+base),
02186                     addReloc(new Const(d))));
02187     | Index8 (d, base, index, ss) =>
02188             // m[ r[ base ] + r[ index ] * ss + d ]
02189             expr = Location::memOf(new Binary(opPlus,
02190                     dis_Reg(24+base),
02191                     new Binary(opPlus,
02192                         new Binary(opMult,
02193                             dis_Reg(24+index),
02194                             new Const(1<<ss)),
02195                         addReloc(new Const(d)))));
02196     | Base8 (d, base) =>
02197             // m[ r[ base] + d ]
02198             // Note: d should be sign extended; we do it here manually
02199             signed char ds8 = d;
02200             expr = Location::memOf(new Binary(opPlus,
02201                     dis_Reg(24+base),
02202                     new Const(ds8)));
02203     | Indir (base) => 
02204             // m[ r[base] ]
02205             expr = Location::memOf(dis_Reg(24+base));
02206     | ShortIndex (d, index, ss) =>
02207             // m[ r[index] * ss + d ]
02208             expr = Location::memOf(new Binary(opPlus,
02209                     new Binary(opMult,
02210                         dis_Reg(24+index),
02211                         new Const(1<<ss)),
02212                     addReloc(new Const(d))));
02213     | IndirMem (d) =>
02214             // [d] (Same as Abs32 using SIB)
02215             expr = Location::memOf(addReloc(new Const(d)));
02216     endmatch
02217     return expr;
02218 }
02219 
02220 /*==============================================================================
02221  * FUNCTION:        dis_Eaddr
02222  * OVERVIEW:        Converts a dynamic address to a Exp* expression.
02223  *                  E.g. %ecx --> r[ 25 ]
02224  * CALLED FROM:     Macros DIS_EADDR32, DIS_EADDR16 and DIS_EADDR8
02225  * PARAMETERS:      pc - the instruction stream address of the dynamic
02226  *                    address
02227  *                  size - size of the operand (important if a register)
02228  * RETURNS:         the Exp* representation of the given Eaddr
02229  *============================================================================*/
02230 Exp* PentiumDecoder::dis_Eaddr(ADDRESS pc, int size)
02231 {
02232     match pc to
02233     | E (mem) =>
02234         return dis_Mem (mem);
02235     | Reg (reg) =>
02236         Exp* e;
02237         switch(size) {
02238             case  8: e = dis_Reg(8+reg); break;
02239             case 16: e = dis_Reg(0+reg); break;
02240             default:
02241             case 32: e = dis_Reg(24+reg); break;
02242         }
02243         return e;
02244     endmatch
02245 }
02246 
02247 /*==============================================================================
02248  * FUNCTION:      isFuncPrologue()
02249  * OVERVIEW:      Check to see if the instructions at the given offset match
02250  *                  any callee prologue, i.e. does it look like this offset
02251  *                  is a pointer to a function?
02252  * PARAMETERS:    hostPC - pointer to the code in question (native address)
02253  * RETURNS:       True if a match found
02254  *============================================================================*/
02255 bool PentiumDecoder::isFuncPrologue(ADDRESS hostPC)
02256 {
02257 #if 0
02258     int locals, regs;
02259     if ((InstructionPatterns::frameless_pro(prog.csrSrc, hostPC, locals, regs))
02260         != NULL)
02261             return true;
02262     if ((InstructionPatterns::struct_ptr(prog.csrSrc, hostPC, locals, regs))
02263         != NULL)
02264             return true;
02265     if ((InstructionPatterns::std_entry(prog.csrSrc, hostPC, locals, regs))
02266         != NULL)
02267             return true;
02268 #endif
02269     return false;
02270 }
02271 
02272 
02273 /**********************************
02274  * These are the fetch routines.
02275  **********************************/   
02276 
02277 /*==============================================================================
02278  * FUNCTION:        getWord
02279  * OVERVIEW:        Returns the word starting at the given address.
02280  * PARAMETERS:      lc - address at which to decode the double
02281  * RETURNS:         the decoded double
02282  *============================================================================*/
02283 Byte PentiumDecoder::getByte (unsigned lc)
02284 /* getByte - returns next byte from image pointed to by lc.  */
02285 {
02286     return *(Byte *)lc;
02287 }
02288 
02289 /*==============================================================================
02290  * FUNCTION:        getWord
02291  * OVERVIEW:        Returns the word starting at the given address.
02292  * PARAMETERS:      lc - address at which to decode the double
02293  * RETURNS:         the decoded double
02294  *============================================================================*/
02295 SWord PentiumDecoder::getWord (unsigned lc)
02296 /* get2Bytes - returns next 2-Byte from image pointed to by lc.  */
02297 {
02298     return (SWord)(*(Byte *)lc + (*(Byte *)(lc+1) << 8));
02299 }
02300 
02301 /*==============================================================================
02302  * FUNCTION:        getDword
02303  * OVERVIEW:        Returns the double starting at the given address.
02304  * PARAMETERS:      lc - address at which to decode the double
02305  * RETURNS:         the decoded double
02306  *============================================================================*/
02307 DWord PentiumDecoder::getDword (unsigned lc)
02308 /* get4Bytes - returns the next 4-Byte word from image pointed to by lc. */
02309 {
02310     lastDwordLc = lc - prog->getTextDelta();
02311     return (DWord)(*(Byte *)lc + (*(Byte *)(lc+1) << 8) + (*(Byte *)(lc+2) << 16) + (*(Byte *)(lc+3) << 24));
02312 }
02313 
02314 
02315 /*==============================================================================
02316  * FUNCTION:       PentiumDecoder::PentiumDecoder
02317  * OVERVIEW:       Constructor. The code won't work without this (not sure why the default constructor won't do...)
02318  * PARAMETERS:     None
02319  * RETURNS:        N/A
02320  *============================================================================*/
02321 PentiumDecoder::PentiumDecoder(Prog* prog) : NJMCDecoder(prog)
02322 {
02323     std::string file = Boomerang::get()->getProgPath() + "frontend/machine/pentium/pentium.ssl";
02324     RTLDict.readSSLFile(file.c_str());
02325 }
02326 
02327 // For now...
02328 int PentiumDecoder::decodeAssemblyInstruction(unsigned, int)
02329 { return 0; }
02330 
02331 /*==============================================================================
02332  * FUNCTION:       genBSFR
02333  * OVERVIEW:       Generate statements for the BSF and BSR series (Bit Scan Forward/Reverse)
02334  * PARAMETERS:     pc: native PC address (start of the BSF/BSR instruction)
02335  *                 reg: an expression for the destination register
02336  *                 modrm: an expression for the operand being scanned
02337  *                 init: initial value for the dest register
02338  *                 size: sizeof(modrm) (in bits)
02339  *                 incdec: either opPlus for Forward scans, or opMinus for Reverse scans
02340  *                 numBytes: number of bytes this instruction
02341  * RETURNS:        true if have to exit early (not in last state)
02342  *============================================================================*/
02343 static int BSFRstate = 0;       // State number for this state machine
02344 void genBSFR(ADDRESS pc, Exp* dest, Exp* modrm, int init, int size,
02345   OPER incdec, int numBytes) {
02346     // Note the horrible hack needed here. We need initialisation code, and an extra branch, so the %SKIP/%RPT won't
02347     // work. We need to emit 6 statements, but these need to be in 3 RTLs, since the destination of a branch has to be
02348     // to the start of an RTL.  So we use a state machine, and set numBytes to 0 for the first two times. That way, this
02349     // instruction ends up emitting three RTLs, each with the semantics we need.
02350     // Note: we don't use pentium.SSL for these.
02351     // BSFR1:
02352     //  pc+0:   zf := 1
02353     //  pc+0:   branch exit condition modrm = 0
02354     // BSFR2:
02355     //  pc+1:   zf := 0
02356     //  pc+1:   dest := init
02357     // BSFR3:
02358     //  pc+2: dest := dest op 1
02359     //  pc+2: branch pc+2 condition modrm@[dest:dest]=0
02360     // exit:
02361 
02362     std::list<Statement*>* stmts = new std::list<Statement*>;
02363     Statement* s;
02364     BranchStatement* b;
02365     switch (BSFRstate) {
02366         case 0:
02367             s = new Assign(
02368                 new IntegerType(1),
02369                 new Terminal(opZF),
02370                 new Const(1));
02371             stmts->push_back(s);
02372             b = new BranchStatement;
02373             b->setDest(pc+numBytes);
02374             b->setCondType(BRANCH_JE);
02375             b->setCondExpr(
02376                 new Binary(opEquals,
02377                     modrm->clone(),
02378                     new Const(0)));
02379             stmts->push_back(b);
02380             break;
02381         case 1:
02382             s = new Assign(
02383                 new IntegerType(1),
02384                 new Terminal(opZF),
02385                 new Const(0));
02386             stmts->push_back(s);
02387             s = new Assign(
02388                 new IntegerType(size),
02389                 dest->clone(),
02390                 new Const(init));
02391             stmts->push_back(s);
02392             break;
02393         case 2:
02394             s = new Assign(
02395                 new IntegerType(size),
02396                 dest->clone(),
02397                 new Binary(incdec,
02398                     dest->clone(),
02399                     new Const(1)));
02400             stmts->push_back(s);
02401             b = new BranchStatement;
02402             b->setDest(pc+2);
02403             b->setCondType(BRANCH_JE);
02404             b->setCondExpr(
02405                 new Binary(opEquals,
02406                     new Ternary(opAt,
02407                         modrm->clone(),
02408                         dest->clone(),
02409                         dest->clone()),
02410                     new Const(0)));
02411             stmts->push_back(b);
02412             break;
02413         default:
02414             // Should never happen
02415             assert(BSFRstate - BSFRstate);
02416     }
02417     result.rtl = new RTL(pc + BSFRstate, stmts);
02418     // Keep numBytes == 0 until the last state, so we re-decode this instruction 3 times
02419     if (BSFRstate != 3-1) {
02420         // Let the number of bytes be 1. This is important at least for setting the fallthrough address for the branch
02421         // (in the first RTL), which should point to the next RTL
02422         result.numBytes = 1;
02423         result.reDecode = true;     // Decode this instuction again
02424     } else {
02425         result.numBytes = numBytes;
02426         result.reDecode = false;
02427     }
02428     if (DEBUG_DECODER)
02429         std::cout << std::hex << pc+BSFRstate << std::dec << ": " <<
02430         "BS" << (init == -1 ? "F" : "R") << (size==32 ? ".od" : ".ow") <<
02431         BSFRstate+1 << "\n";
02432     if (++BSFRstate == 3)
02433         BSFRstate = 0;      // Ready for next time
02434         
02435 }
02436 
02437 
02438 Exp *PentiumDecoder::addReloc(Exp *e)
02439 {
02440     if (lastDwordLc != (unsigned)-1)
02441         e = prog->addReloc(e, lastDwordLc);
02442     return e;
02443 }
02444
Generated on Tue Sep 19 21:18:16 2006 for Boomerang by  doxygen 1.4.6